GitHub - inaved-semicon/SDSPI-DFT: Complete production-grade ASIC Design-for-Testability (DFT), ATPG, and Gate-Level Simulation (GLS) flow for a SD Card Controller design using the Cadence toolchain.

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Name		Name	Last commit message	Last commit date
Latest commit History 23 Commits
COMP_SCAN		COMP_SCAN
CONSTRAINTS		CONSTRAINTS
RTL		RTL
SCAN		SCAN
SYNTHESIS		SYNTHESIS

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Complete production-grade ASIC Design-for-Testability (DFT), ATPG, and Gate-Level Simulation (GLS) flow for a SD Card Controller design using the Cadence toolchain.

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