Popular repositories Loading

1. open-source-dft-flow open-source-dft-flow Public

   End-to-end FSM Design-for-Test (DFT) flow using Yosys and Fault including synthesis, ATPG, scan chain, JTAG, and simulation.

   Verilog 4 2

2. OpenSource-PDK-Libraries OpenSource-PDK-Libraries Public

   Collection of open-source ASIC technology libraries, standard-cell databases, and PDK resources for VLSI design, synthesis, DFT, STA, and physical implementation flows.

   Verilog 1

3. SDSPI-DFT SDSPI-DFT Public

   Complete production-grade ASIC Design-for-Testability (DFT), ATPG, and Gate-Level Simulation (GLS) flow for a SD Card Controller design using the Cadence toolchain.

   Verilog

4. RISC-V-FPGA-IP-Development RISC-V-FPGA-IP-Development Public

   C

5. SOCX SOCX Public

   DFT Flow on a Multi-Clock SoC using Cadence Genus & Modus: Scan Insertion, DFT DRC Analysis, Scan Chain Stitching, ATPG Pattern Generation, Fault Coverage Evaluation, and Gate-Level Verification.

   Verilog

6. RTL-TO-GDSII RTL-TO-GDSII Public

   End-to-end ASIC implementation flow using SKY130 and open-source EDA tools, including simulation, synthesis, DFT, ATPG, JTAG, STA, floorplanning, placement, CTS, routing, and GDS generation.

   Verilog