This repository contains my work on a hardware implementation of the International Data Encryption Algorithm (IDEA) written in VHDL.
The project was completed as part of a university-level hardware design course and focuses on translating a cryptographic algorithm into synthesizable RTL suitable for FPGA-oriented design.
Only high-level information is provided here. Detailed implementations and solutions are intentionally not described, as this work was carried out within the context of an academic course.
The work involved implementing and validating the IDEA encryption algorithm using multiple hardware design approaches, with increasing emphasis on resource efficiency and hardware constraints.
Across the project, the following aspects were addressed:
- Mapping an algorithmic specification to RTL
- Modular VHDL design
- Use of arithmetic building blocks (XOR, modular addition, modular multiplication)
- Control and datapath separation
- Verification using simulation and testbenches
- FPGA-oriented design considerations
The repository is organized into several independent project variants, each representing a different architectural approach to the same algorithm.
At a high level, these variants range from:
- A direct, algorithm-oriented implementation
- To increasingly resource-conscious and hardware-oriented designs
No detailed architectural descriptions are included.
- Hardware Description Language: VHDL
- FPGA Design Tools: Xilinx ISE
- Simulation: Behavioral RTL simulation
- Design Style: Modular, synthesizable RTL
- Target Context: FPGA-oriented hardware design
This project demonstrates experience with:
- RTL design in VHDL
- Cryptographic hardware concepts
- FPGA design workflows
- Simulation-based verification
- Structured hardware design methodology
This repository is presented as a technical portfolio overview. Detailed solutions, internal architectures, and course-specific implementation details are intentionally omitted in accordance with academic integrity and course policies.