Pinned Loading

1. ATM-Packetizer-AAL1 ATM-Packetizer-AAL1 Public

   VHDL-based simulation of a simplified ATM (AAL1) packetizer, focusing on digital design, testbenches, and waveform verification in ModelSim.

2. Basys3-FPGA-Signal-Processing-FIR-Filter Basys3-FPGA-Signal-Processing-FIR-Filter Public

   This project implements a fixed-point FIR filteron FPGA, starting from MATLAB modeling and finishing with the RTL implementation.

   VHDL

3. Basys3-FPGA-Stopwatch Basys3-FPGA-Stopwatch Public

   In this project, I constructed on paper and built a stop timer from scratch. The timer works based on the middle and right buttons of the Basys3 board.

   VHDL

4. Basys3-FPGA-UART-Transceiver Basys3-FPGA-UART-Transceiver Public

   VHDL UART transmitter/receiver for the Basys3 FPGA, verified in simulation and tested over serial communication with PuTTY.

   VHDL

5. RISC-V-CPU-Core RISC-V-CPU-Core Public

   TL-Verilog coursework from the edX "Building a RISC-V CPU Core" course.

   Verilog

6. Spartan-3E-FPGA-IDEA-Encryption-Algorithm Spartan-3E-FPGA-IDEA-Encryption-Algorithm Public

   VHDL Project on implementing the IDEA Encryption Algorithm on a Spartan-3E FPGA