fix(rvv decode): add inst[14:12] constraint on vlm/vsm

[skyhgzsh]

No description provided.

[Copilot]

Pull request overview

Tightens RVV load/store decode patterns so vlm/vsm (mask load/store) only match when inst[14:12] (the width/funct3 field for vector loads/stores) is 000, preventing reserved/other-width encodings from being incorrectly executed as mask operations.

Changes:

• Constrain vlm decode pattern to require inst[14:12] == 000 (direct + MMU paths).
• Constrain vsm decode pattern to require inst[14:12] == 000 (direct + MMU paths).

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[github-actions]

NEMU Performance Results - XS Interpreter

Test	Guest Instructions	Host Instructions	Estimated Host Throughput (instr/s)	Actual NEMU Throughput (instr/s)	Baseline Host Instructions	Baseline Actual NEMU Throughput (instr/s)	Change vs Baseline (Instructions)	Change vs Baseline (Throughput)
bitmanip.bin	1.385e+05	5.189e+07	2.669e+07	3.133e+07	5.190e+07	3.255e+07	+0.00%	-3.75%
coremark-riscv64-xs-rv64gc-o2.bin	3.354e+06	1.752e+08	1.914e+08	1.859e+08	1.752e+08	1.842e+08	-0.00%	+0.92%
coremark-riscv64-xs-rv64gc-o3.bin	3.394e+06	1.747e+08	1.943e+08	1.991e+08	1.747e+08	1.905e+08	+0.00%	+4.50%
coremark-riscv64-xs-rv64gcb-o3.bin	3.035e+06	1.718e+08	1.766e+08	1.843e+08	1.718e+08	1.793e+08	-0.00%	+2.76%
amtest-riscv64-xs.bin	1.587e+04	8.704e+06	1.824e+07	1.646e+07	8.702e+06	1.446e+07	-0.03%	+13.90%
aliastest-riscv64-xs.bin	1.376e+03	7.706e+06	1.786e+06	3.163e+06	7.704e+06	3.238e+06	-0.03%	-2.30%
softprefetchtest-riscv64-xs.bin	2.643e+03	7.754e+06	3.409e+06	9.473e+06	7.752e+06	6.048e+06	-0.03%	+56.63%
zacas-riscv64-xs.bin	6.470e+04	1.222e+07	5.296e+07	1.784e+07	1.222e+07	1.990e+07	+0.00%	-10.34%
linux-hello	7.545e+07	1.882e+10	4.010e+07	4.881e+07	1.882e+10	4.936e+07	-0.00%	-1.10%

NEMU Performance Results - XS Ref Shared Object

Test	Guest Instructions	Host Instructions	Estimated Host Throughput (instr/s)	Actual NEMU Throughput (instr/s)	Baseline Host Instructions	Baseline Actual NEMU Throughput (instr/s)	Change vs Baseline (Instructions)	Change vs Baseline (Throughput)
bitmanip.bin	1.385e+05	1.118e+09	1.239e+06	7.900e+05	1.118e+09	7.000e+05	+0.00%	+12.86%
coremark-riscv64-xs-rv64gc-o2.bin	3.354e+06	6.961e+09	4.819e+06	3.005e+06	6.961e+09	3.353e+06	-0.00%	-10.37%
coremark-riscv64-xs-rv64gc-o3.bin	3.394e+06	6.996e+09	4.852e+06	3.034e+06	6.995e+09	3.215e+06	-0.00%	-5.62%
coremark-riscv64-xs-rv64gcb-o3.bin	3.035e+06	6.555e+09	4.630e+06	2.961e+06	6.555e+09	2.857e+06	+0.00%	+3.64%
amtest-riscv64-xs.bin	1.588e+04	3.707e+07	4.283e+06	1.612e+06	3.707e+07	1.665e+06	+0.00%	-3.17%
aliastest-riscv64-xs.bin	1.379e+03	5.088e+06	2.710e+06	6.905e+05	5.088e+06	6.426e+05	+0.00%	+7.46%
softprefetchtest-riscv64-xs.bin	2.646e+03	7.392e+06	3.580e+06	1.155e+06	7.392e+06	1.036e+06	+0.00%	+11.52%
zacas-riscv64-xs.bin	6.471e+04	1.399e+08	4.627e+06	1.783e+06	1.399e+08	2.077e+06	-0.00%	-14.18%
linux-hello	7.522e+07	6.802e+11	1.106e+06	1.015e+06	6.802e+11	9.842e+05	-0.00%	+3.16%

• Host Instructions is measured by DynamoRIO's inscount client.
• Estimated Host Throughput assumes a fixed 4GHz CPU and IPC=2.5.
• Actual NEMU Throughput is a single native NEMU run and may vary with host CPU performance.
• Baseline columns are populated on pull_request runs when the PR base contains the same defconfig.
• Change vs Baseline (Instructions) is computed from host instruction count; positive means fewer host instructions than baseline.
• Change vs Baseline (Throughput) is computed from native throughput; positive means faster than baseline.

[poemonsense]

I don't know the vector load/store instructions and should not approve this