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configs: Fix difftest init bug in single-thread Sim#953

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configs: Fix difftest init bug in single-thread Sim#953
xk23333 wants to merge 1 commit into
OpenXiangShan:xs-devfrom
xk23333:feature/fix-single-thread-difftest-bug

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@xk23333 xk23333 commented Jul 11, 2026

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Problem Description

When running GEM5 simulation with --enable-difftest in single-core mode, the simulation aborts immediately with a memory access error.

Error Log:

**** REAL SIMULATION ****
build/RISCV/sim/simulate.cc:194: info: Entering event queue @ 0.  Starting simulation...
gem5.opt: src/cpu/difftest/ref.c:78: difftest_memcpy: Assertion `guest_to_host(nemu_addr) != NULL' failed.
Program aborted at tick 66267

Root Cause Analysis

The issue stems from a configuration mismatch between GEM5 and the NEMU reference model regarding memory deduplication (mem_dedup).

  1. NEMU Side: The NEMU reference library is compiled with CONFIG_ENABLE_MEM_DEDUP=1. This configuration requires the memory to be passed from the DUT (GEM5) rather than allocated internally by NEMU.
  2. GEM5 Side: In configs/common/xiangshan.py, the config_difftest() function handles configuration differently for multi-core/SMT and single-core modes:
    • Multi-core/SMT: Correctly sets sys.enable_mem_dedup = True and cpu.enable_mem_dedup = True.
    • Single-core: The lines enabling mem_dedup were commented out.

Because enable_mem_dedup was disabled in single-core mode, GEM5 did not pass the memory pointer to NEMU as expected. Consequently, NEMU failed to map the guest address, leading to the difftest_memcpy assertion failure.

Solution

Uncomment the enable_mem_dedup settings in the single-core branch of config_difftest() to ensure consistency with the multi-core configuration and the NEMU build flags.

Code Changes in configs/common/xiangshan.py:

# Before:
        else:
            # sys.enable_mem_dedup = True
            # cpu_list[0].enable_mem_dedup = True
            cpu_list[0].enable_difftest = True
            ...

# After:
        else:
            sys.enable_mem_dedup = True
            cpu_list[0].enable_mem_dedup = True
            cpu_list[0].enable_difftest = True
            ...

Verification

After applying this fix, single-core simulations with --enable-difftest start successfully without triggering the guest_to_host assertion failure.

Summary by CodeRabbit

  • Bug Fixes
    • Enabled memory deduplication for single-core, non-SMT configurations, improving consistency with multi-core setups.

Signed-off-by: xuke <24212020033@m.fudan.edu.cn>
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coderabbitai Bot commented Jul 11, 2026

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Review Change Stack

No actionable comments were generated in the recent review. 🎉

ℹ️ Recent review info
⚙️ Run configuration

Configuration used: defaults

Review profile: CHILL

Plan: Pro

Run ID: 568c26eb-35b9-41d7-884b-555b4474c5e1

📥 Commits

Reviewing files that changed from the base of the PR and between 45bed11 and 54ac3bb.

📒 Files selected for processing (1)
  • configs/common/xiangshan.py

📝 Walkthrough

Walkthrough

The single-core, non-SMT difftest configuration now enables memory deduplication for both the system and its first CPU.

Changes

Difftest memory deduplication

Layer / File(s) Summary
Single-core deduplication configuration
configs/common/xiangshan.py
The non-multi-core branch now sets sys.enable_mem_dedup and cpu_list[0].enable_mem_dedup to True.

Estimated code review effort: 1 (Trivial) | ~5 minutes

🚥 Pre-merge checks | ✅ 5
✅ Passed checks (5 passed)
Check name Status Explanation
Description Check ✅ Passed Check skipped - CodeRabbit’s high-level summary is enabled.
Title check ✅ Passed The title clearly summarizes the main fix: a difftest initialization bug in single-threaded simulation.
Docstring Coverage ✅ Passed No functions found in the changed files to evaluate docstring coverage. Skipping docstring coverage check.
Linked Issues check ✅ Passed Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check ✅ Passed Check skipped because no linked issues were found for this pull request.
✨ Finishing Touches
🧪 Generate unit tests (beta)
  • Create PR with unit tests

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@jueshiwenli jueshiwenli added the perf-align Trigger Align BTB performance CI label Jul 13, 2026
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