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ASoC: SOF: Intel: hda: follow strict BDLE address alignment for ACE4#5684

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ASoC: SOF: Intel: hda: follow strict BDLE address alignment for ACE4#5684
kv2019i wants to merge 1 commit intothesofproject:topic/sof-devfrom
kv2019i:202603-ace4-strict-bdle-alignment

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@kv2019i kv2019i commented Mar 5, 2026

Intel ACE4 based products require host to strictly follow HDA spec guidance on BDLE address alignment. Each BDLE address must be aligned to 128 bytes, and given ALSA periods are directly mapped to BDLEs, period size must be 128 aligned as well.

Reported-by: Peter Ujfalusi peter.ujfalusi@linux.intel.com

Intel ACE4 based products require host to strictly follow HDA
spec guidance on BDLE address alignment. Each BDLE address must be
aligned to 128 bytes, and given ALSA periods are directly mapped
to BDLEs, period size must be 128 aligned as well.

Reported-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
@kv2019i kv2019i requested a review from ujfalusi March 5, 2026 17:58
snd_pcm_hw_constraint_step(substream->runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 4);
if (chip_info->hw_ip_version >= SOF_INTEL_ACE_4_0)
snd_pcm_hw_constraint_step(substream->runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
SOF_HDA_BDLE_ADDRESS_ALIGNMENT);
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you also need to fix legacy HDA in sound/hda/controllers/intel.c and add AZX_DCAPS_NO_ALIGN_BUFSIZE to both NVL and NVL_S, probably by:

#define AZX_DCAPS_INTEL_NVL (AZX_DCAPS_INTEL_LNL | AZX_DCAPS_NO_ALIGN_BUFSIZE)

/* SDxFIFOS FIFOS */
#define SOF_HDA_SD_FIFOSIZE_FIFOS_MASK GENMASK(15, 0)

/* HDA BDLE size constraints */
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the alignment is for the address within the BDLE, iow to the start of a period.

snd_pcm_hw_constraint_step(substream->runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
SOF_HDA_BDLE_ADDRESS_ALIGNMENT);
else
/* minimum as per HDA spec */
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I would remove this sentence and/or replace it with something which is correct (also for the legacy comment block, that is wrong in the same way)

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