sfuphantom · seekbot · Jun 11, 2022
diff --git a/TSAL_AIL/History/Sheet1.~(1).SchDoc.Zip b/TSAL_AIL/History/Sheet1.~(1).SchDoc.Zip
diff --git a/TSAL_AIL/History/Sheet1.~(10).SchDoc.Zip b/TSAL_AIL/History/Sheet1.~(10).SchDoc.Zip
diff --git a/TSAL_AIL/History/Sheet1.~(11).SchDoc.Zip b/TSAL_AIL/History/Sheet1.~(11).SchDoc.Zip
diff --git a/TSAL_AIL/History/Sheet1.~(12).SchDoc.Zip b/TSAL_AIL/History/Sheet1.~(12).SchDoc.Zip
diff --git a/TSAL_AIL/History/Sheet1.~(13).SchDoc.Zip b/TSAL_AIL/History/Sheet1.~(13).SchDoc.Zip
diff --git a/TSAL_AIL/History/Sheet1.~(14).SchDoc.Zip b/TSAL_AIL/History/Sheet1.~(14).SchDoc.Zip
diff --git a/TSAL_AIL/History/Sheet1.~(15).SchDoc.Zip b/TSAL_AIL/History/Sheet1.~(15).SchDoc.Zip
diff --git a/TSAL_AIL/History/Sheet1.~(6).SchDoc.Zip b/TSAL_AIL/History/Sheet1.~(6).SchDoc.Zip
diff --git a/TSAL_AIL/History/Sheet1.~(7).SchDoc.Zip b/TSAL_AIL/History/Sheet1.~(7).SchDoc.Zip
diff --git a/TSAL_AIL/History/Sheet1.~(8).SchDoc.Zip b/TSAL_AIL/History/Sheet1.~(8).SchDoc.Zip
diff --git a/TSAL_AIL/History/Sheet1.~(9).SchDoc.Zip b/TSAL_AIL/History/Sheet1.~(9).SchDoc.Zip
diff --git a/TSAL_AIL/History/TSAL_AIL PCB.~(1).PcbDoc.Zip b/TSAL_AIL/History/TSAL_AIL PCB.~(1).PcbDoc.Zip
diff --git a/TSAL_AIL/History/TSAL_AIL PCB.~(10).PcbDoc.Zip b/TSAL_AIL/History/TSAL_AIL PCB.~(10).PcbDoc.Zip
diff --git a/TSAL_AIL/History/TSAL_AIL PCB.~(11).PcbDoc.Zip b/TSAL_AIL/History/TSAL_AIL PCB.~(11).PcbDoc.Zip
diff --git a/TSAL_AIL/History/TSAL_AIL PCB.~(12).PcbDoc.Zip b/TSAL_AIL/History/TSAL_AIL PCB.~(12).PcbDoc.Zip
diff --git a/TSAL_AIL/History/TSAL_AIL PCB.~(13).PcbDoc.Zip b/TSAL_AIL/History/TSAL_AIL PCB.~(13).PcbDoc.Zip
diff --git a/TSAL_AIL/History/TSAL_AIL PCB.~(14).PcbDoc.Zip b/TSAL_AIL/History/TSAL_AIL PCB.~(14).PcbDoc.Zip
diff --git a/TSAL_AIL/History/TSAL_AIL PCB.~(15).PcbDoc.Zip b/TSAL_AIL/History/TSAL_AIL PCB.~(15).PcbDoc.Zip
diff --git a/TSAL_AIL/History/TSAL_AIL PCB.~(16).PcbDoc.Zip b/TSAL_AIL/History/TSAL_AIL PCB.~(16).PcbDoc.Zip
diff --git a/TSAL_AIL/History/TSAL_AIL PCB.~(2).PcbDoc.Zip b/TSAL_AIL/History/TSAL_AIL PCB.~(2).PcbDoc.Zip
diff --git a/TSAL_AIL/History/TSAL_AIL PCB.~(3).PcbDoc.Zip b/TSAL_AIL/History/TSAL_AIL PCB.~(3).PcbDoc.Zip
diff --git a/TSAL_AIL/History/TSAL_AIL PCB.~(4).PcbDoc.Zip b/TSAL_AIL/History/TSAL_AIL PCB.~(4).PcbDoc.Zip
diff --git a/TSAL_AIL/History/TSAL_AIL PCB.~(5).PcbDoc.Zip b/TSAL_AIL/History/TSAL_AIL PCB.~(5).PcbDoc.Zip
diff --git a/TSAL_AIL/History/TSAL_AIL PCB.~(6).PcbDoc.Zip b/TSAL_AIL/History/TSAL_AIL PCB.~(6).PcbDoc.Zip
diff --git a/TSAL_AIL/History/TSAL_AIL PCB.~(7).PcbDoc.Zip b/TSAL_AIL/History/TSAL_AIL PCB.~(7).PcbDoc.Zip
diff --git a/TSAL_AIL/History/TSAL_AIL PCB.~(8).PcbDoc.Zip b/TSAL_AIL/History/TSAL_AIL PCB.~(8).PcbDoc.Zip
diff --git a/TSAL_AIL/History/TSAL_AIL PCB.~(9).PcbDoc.Zip b/TSAL_AIL/History/TSAL_AIL PCB.~(9).PcbDoc.Zip
diff --git a/TSAL_AIL/History/TSAL_AIL.~(1).PrjPcb.Zip b/TSAL_AIL/History/TSAL_AIL.~(1).PrjPcb.Zip
diff --git a/TSAL_AIL/History/TSAL_AIL.~(3).PrjPcb.Zip b/TSAL_AIL/History/TSAL_AIL.~(3).PrjPcb.Zip
diff --git a/TSAL_AIL/History/TSAL_AIL.~(4).PrjPcb.Zip b/TSAL_AIL/History/TSAL_AIL.~(4).PrjPcb.Zip
diff --git a/TSAL_AIL/History/TSAL_AIL.~(5).PrjPcb.Zip b/TSAL_AIL/History/TSAL_AIL.~(5).PrjPcb.Zip
diff --git a/TSAL_AIL/Project Logs for TSAL_AIL/TSAL_AIL PCB PCB ECO 2022-06-05 11-46-23 PM.LOG b/TSAL_AIL/Project Logs for TSAL_AIL/TSAL_AIL PCB PCB ECO 2022-06-05 11-46-23 PM.LOG
@@ -0,0 +1,5 @@
+Change Net Name : Old Net Name=LV GND New Net Name=Emitter
+Change Net Name : Old Net Name=NetQ1_1 New Net Name=Anode
+Change Net Name : Old Net Name=NetQ1_2 New Net Name=Cathode
+Change Net Name : Old Net Name=NetQ1_4 New Net Name=Collector
+Added Room: Name=Sheet1
diff --git a/TSAL_AIL/Project Logs for TSAL_AIL/TSAL_AIL PCB PCB ECO 2022-06-05 9-59-02 PM.LOG b/TSAL_AIL/Project Logs for TSAL_AIL/TSAL_AIL PCB PCB ECO 2022-06-05 9-59-02 PM.LOG
diff --git a/TSAL_AIL/Project Logs for TSAL_AIL/TSAL_AIL PCB PCB ECO 2022-06-06 12-00-26 AM.LOG b/TSAL_AIL/Project Logs for TSAL_AIL/TSAL_AIL PCB PCB ECO 2022-06-06 12-00-26 AM.LOG
@@ -0,0 +1,3 @@
+Change Net Name : Old Net Name=NetDS1_2 New Net Name=HV ON
+Change Net Name : Old Net Name=NetDS2_2 New Net Name=LV ON
+Added Room: Name=Sheet1
diff --git a/TSAL_AIL/Sheet1.SchDoc b/TSAL_AIL/Sheet1.SchDoc
diff --git a/TSAL_AIL/TSAL_AIL PCB.PcbDoc b/TSAL_AIL/TSAL_AIL PCB.PcbDoc
diff --git a/TSAL_AIL/TSAL_AIL.BomDoc b/TSAL_AIL/TSAL_AIL.BomDoc