refactor opcode circuit dispatching and vector allocation#1222
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refactor opcode circuit dispatching and vector allocation#1222
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better empty handling remove DispatchBucket and replace by vector refactor on insn usage in instruction fmt remove ecall dummy refactor indent misc: naming cosmetics step streaming to dispatcher directly fmt & cleanup minimize code change line inline streaming injection
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### Design rationales Refactor shard cycle logic into pre-flight tracer in low overhead way. With that, in preflight tracer we only update `next_access` with cross-shard memory access. This optimization bring much gain on preflight executor performance ### benchmark test on `23817600` | Stage | Before | After | |-------------------------------------|-----------------------|-----------------------| |e2e| 195s | 161s | | emulator.preflight-execute (total) | 39.5 s · 20.10% | 10.4 s · 6.44% | | emulator.new-preflight-tracer | | 3.01 ms · 0.00% | | emulator.init_mem | | 9.94 ms · 0.01% |
kunxian-xia
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Jan 19, 2026
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This is preparation of #1220 to support single circuit subscribe to multi riscv opcodes
Change summary
emulator emit steps -> single vector -> then dispatcher multi vectorto new flowemulator emit steps -> multi vector, save one redundant allocationassign_opcode!(ADD, AddInstruction<E>, add_config);->assign_opcode!(AddInstruction<E>, add_config);and dispatch deal with routing for usBenchmark
test with
23817600block, e2e remain no changeremain no change which is expected. Because 1st shard we still need to allocated vector, while shard > 0 pipeline gpu proving time is dominated
For detail breakdown
assign_opcode_circuitaround 10% improvement