Implement mixed-size access in UM promising model#98
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This is good work! There are still some kinks to iron out both in the fiddly part of the mixed-semantics and in general organization, but I think this is close to being mergeable
- Msg.t: dependent record with `val : bv (8 * size)` so all messages share one list - Multi-byte reads: single observation point per load - Exclusive monitor: stores LDXR addr/size, mismatch is non-deterministic (ARM ARM B2.12) - CBitvector: vm_compute-friendly bv_eq_dec/countable/finite replacing stdpp's opaque versions - GenPromising: mEvent_eqb / remove_dups_by to bypass eq_dec blocking under vm_compute
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| - [tr]: snapshot time | ||
| - [mv]: byte value from the snapshot | ||
| - [tw]: write timestamp from the snapshot *) | ||
| Definition read_fwd (macc : mem_acc) (fwdb : gmap address FwdItem.t) |
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Move this outside Memory module and split fwdbank and memory
| End Memory. | ||
| Import (hints) Memory. | ||
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| Module FwdItem. |
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It should be after Memory module. (It should patch the results from Memory itself.)
| let resolved := | ||
| map (λ '(a, (sv, tw)), read_fwd macc fwdb init mem t a sv tw) | ||
| (zip addrs snap) in | ||
| Some (bv_of_bytes (8 * size) (map (λ '(v, _, _), v) resolved), |
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Reduce the number of bitvector <-> list casting.
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Summary
Msg.tis now a dependent record withval : bv (8 * size)so all messages live in one listbv_eq_dec_compute,bv_countable_compute,bv_finite_computein CBitvector.v: vm_compute-friendly replacements for stdpp's opaquebv_eq_dec/bv_countable/bv_finite, whosebv_wf_pi(Qed) blocks reduction of equality proofs