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TinyTPU v1.0 - Initial Release: Real SystemVerilog TPU Simulator

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@deaneeth deaneeth released this 13 Jul 12:36
v1.0
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TinyTPU v1.0 - Initial Release: Real SystemVerilog TPU Simulator

TinyTPU v1.0 is the first stable release of a browser-based TPU simulator and systolic array visualizer. It runs a real, synthesizable 4x4 weight-stationary systolic array written in SystemVerilog, compiled through Verilator and Emscripten to WebAssembly, then visualized live in the browser.

The core promise is simple: no JavaScript reimplementation of matrix multiplication. The React interface reads cycle-by-cycle state from the compiled RTL through the documented debug output bus, so every processing element, activation, partial sum, and output value is tied back to the hardware model.

Live visualizer: https://tiny-tpu.vercel.app
Source code: https://github.com/deaneeth/tiny-tpu
How it works: https://tiny-tpu.vercel.app/docs/how-it-works

What ships in v1.0

  • A real 4x4 systolic array for matrix multiplication

    • 16 processing elements arranged in a weight-stationary dataflow
    • Signed int8 matrix inputs
    • Signed 32-bit accumulators
    • Matrix B loaded as stationary weights
    • Matrix A streamed from the west edge with row-skewed timing
    • Results drained from the south edge

  • Synthesizable SystemVerilog RTL

    • rtl/pe.sv for the MAC processing element
    • rtl/systolic_array.sv for the 4x4 PE grid
    • rtl/controller.sv for the IDLE -> LOAD_WEIGHTS -> STREAM -> DRAIN FSM
    • rtl/tiny_tpu_top.sv for the top-level wrapper and debug output bus

  • WebAssembly hardware execution in the browser

    • Verilator compiles the RTL into a cycle-accurate C++ model
    • Emscripten compiles the C++ model into tiny_tpu.wasm
    • The browser runs the compiled hardware model directly
    • The frontend visualizer consumes hardware-derived CycleState objects

  • Interactive learning interface

    • L1: single MAC cell view
    • L2: full 4x4 systolic array view
    • L3: tiled matrix multiplication view for matrices larger than the array
    • Matrix input controls for experimenting with signed int8 values
    • Cycle playback controls for stepping through the computation

  • Verification and release checks

    • RTL linted with Verilator
    • cocotb tests checked against a NumPy golden model
    • WASM build verified through CI
    • Astro, React, and TypeScript frontend build verified through CI
    • GitHub Actions passed for Web CI, RTL CI, and WASM Build on the v1.0 tag

Why this release matters

Most hardware education demos show an animation of the idea. TinyTPU shows the implementation. The visualizer is downstream of the compiled RTL, so the project is useful for people learning computer architecture, AI accelerator design, matrix multiplication hardware, systolic arrays, Verilator, WebAssembly, and frontend hardware visualization.

If you are searching for a visual TPU simulator, a SystemVerilog systolic array example, or a real RTL-to-browser WebAssembly hardware demo, this release is the stable starting point.

Quick start

Open the live visualizer:

https://tiny-tpu.vercel.app/app

Or build locally from source:

git clone https://github.com/deaneeth/tiny-tpu.git
cd tiny-tpu
source ~/.venvs/tinytpu/bin/activate
verilator --lint-only -Wall rtl/*.sv
bash wasm/build.sh
cd web
pnpm install
pnpm dev

Repository map

tiny-tpu/
├─ rtl/        SystemVerilog source of truth
├─ sim/        cocotb tests and NumPy golden model
├─ wasm/       Verilator C++ harness and Emscripten bindings
├─ web/        Astro + React visualizer
└─ docs/       state schema and architecture notes

Search-focused topics covered

  • TPU simulator
  • systolic array visualizer
  • SystemVerilog matrix multiplication
  • WebAssembly hardware simulation
  • Verilator to WASM pipeline
  • AI accelerator architecture
  • weight-stationary dataflow
  • cycle-accurate RTL visualization

Full changelog

https://github.com/deaneeth/tiny-tpu/commits/v1.0

License

MIT License. Free to use, learn from, modify, and build on.

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