CPID: parse cpu feaures depending on the register index#64
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guoren83 merged 2 commits intoXUANTIE-RV:masterfrom Apr 10, 2026
Merged
CPID: parse cpu feaures depending on the register index#64guoren83 merged 2 commits intoXUANTIE-RV:masterfrom
guoren83 merged 2 commits intoXUANTIE-RV:masterfrom
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Change-Id: I1fcaee925e4068bc46faab374431bece55e065ab Signed-off-by: shuangluo.zhang <shuangluo.zhang@alibaba-inc.com> Co-authored-by: tian.he <ht412853@alibaba-inc.com>
Change-Id: I83a4386046a9341650a7351fab94d8869bffd7f5 Co-authored-by: tian.he <ht412853@alibaba-inc.com>
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Since the read from CPID register may not always from index 0 to 6 at any time, it will lead to the error info for cpu_ver and cpu_type. This change adds the register index check before parsing.
Furthermore, the CPID spec defines 7 registers available while 2 of them are useful for zsb now, this change also minimize the register access for efficiency.
I have some basic manual test on FPGA platforms with print out after the parse. Here is the test code and results:
Code:
printf("cpu %x %x %x\n", cpu_type, cpu_ver, cpu_tnmodel);
Results:
FPGA --> print out
//C908V R1S0P12. --> cpu 5 100c 0
//R908FDV-CP-XT R0S0P15. --> cpu 2 f 0
//C920v3-CP-XT R3S1P5. --> cpu 3 3045 0
//C907FDVM-rv32 R0S1P0. --> cpu 6 40 0
//C907FDVM-rv64 R0S0P16. --> cpu 6 10 0
//C908X-CP-XT R0S0P9. --> cpu 5 9 1
As this change affects all platforms that supported by zsb, more tests for coverage are necessary.