RISC-V

Minimalistic RISC-V processor using a 5-Stage MIPS pipeline implemented in Verilog as a vivado project to run on FPGA dev board PYNQ-Z2.

Base Instruction set RV32I Version 2.1 as specified in The RISC-V Instruction Set Manual Volume I Unprivileged Architecture Version 20250508 (Link as of 26/08/2025)

The following subchapters will serve as an extraction of the relevant information from the ISA manual.

Instructions

Minimal set of instructions as specified in Manual

RV32I contains 40 unique instructions, though a simple implementation might cover the ECALL/EBREAK instructions with a single SYSTEM hardware instruction that always traps and might be able to implement the FENCE instruction as a NOP, reducing base instruction count to 38 total.

• Implement ECALL/EBREAK as SYSTEM instruction that always traps
• Implement FENCE as NOP

Subsets of the base integer ISA might be useful for pedagogical purposes, but the base has been defined such that there should be little incentive to subset a real hardware implementation beyond omitting support for misaligned memory accesses and treating all SYSTEM instructions as a single trap.

• Omit support for misaligned memory access
• Implement all SYSTEM instructions as a single trap

Registers

• 32 Registers each 32 bits wide
• Register x0 is hardwired with all bits 0
• Registers x1 - x31 are general purpose an can each be interpreted as
  • Collection of boolean values
  • Unsigned binary integer
  • Two's complement signed binary integer
• Additional register PC (program counter) holds the address of the current instruction
• Standard software calling convention:
  • x2 stack pointer
  • x1 holds the return address of a call
  • x5 is available as an alternative llink register

Instruction Formats

Four core instruction formats R,I,S,U plus additional immediate handling variants B,J

• Source registers rs1, rs2 and destination register rd are always at the same position
• Immediates are always sign-extended and generally packed towards the left. The sign is always bit 31

Integer Computational Instructions

• No arithmetic exceptions

Register-Immediate operations

encoded using I-Type

• ADDI
• SLTI
• SLTIU
• ANDI
• ORI
• XORI
• SLLI
• SRLI
• SRAI
• LUI
• AUIPC

Register-Register operations

encoded using R-Type

• ADD
• SLT
• SLTU
• AND
• OR
• XOR
• SLL
• SRL
• SUB
• SRA

NOP

Advances PC. Implemented through ADDI 0x, 0x, 0

Control Transfer Instructions

Unconditional Jumps

• JAL
• JALR

Conditional Branches

• BEQ
• BNE
• BLT
• BLTU
• BGE
• BGEU

Load and Store instructions

• LW
• LH
• LHU
• LBU
• SW
• SH
• SB

Memory ordering Instructions

• FENCE

Enviroment Call and Breakpoints

• ECALL
• EBREAK