Update fearless_simd requirement from 0.3.0 to 0.4.0

[dependabot]

Updates the requirements on fearless_simd to permit the latest version.

Release notes

Sourced from fearless_simd's releases.

v0.4.0

Crates.io | Docs

This release has an [MSRV][] of 1.88.

Added

• All vector types now implement Index and IndexMut. (#112[] by [@​Ralith][])
• 256-bit vector types now use native AVX2 intrinsics on supported platforms. (#115[] by [@​valadaptive][])
• 8-bit integer multiplication is now implemented on x86. (#115[] by [@​valadaptive][])
• New native-width associated types: f64s and mask64s. (#125[] by [@​valadaptive][])
• The bitwise "not" operation on integer vector types. (#130[] by [@​valadaptive][])
• The from_fn method on vector types. (#137[] by [@​valadaptive][])
• The load_interleaved and store_interleaved operations now use native intrinsics on x86, instead of using the fallback implementations. (#140[] by [@​valadaptive][])
• Add support for relaxed_simd operations in WebAssembly. (#143[] by [@​valadaptive][])
• The ceil and round_ties_even operations on floating-point vector types. (Rust's round operation rounds away from zero in the case of ties. Many architectures do not natively implement that behavior, so it's omitted.) (#145[] by [@​valadaptive][])
• A prelude module, which exports all the traits in the library but not the types. (#149[] by [@​valadaptive][])
• The any_true, all_true, any_false, and all_false methods on mask types. (#141[] by [@​valadaptive][])
• Documentation for most traits, vector types, and operations. (#154[] by [@​valadaptive][])
• A "shift left by vector" operation, to go with the existing "shift right by vector". (#155[] by [@​valadaptive][])
• "Precise" float-to-integer conversions, which saturate out-of-bounds results and convert NaN to 0 across all platforms. (#167[] by [@​valadaptive][])
• Add the slide and slide_within_blocks methods for shifting elements within a vector. (#164[] by [@​valadaptive][])
• The Level::is_fallback method, which lets you check if the current SIMD level is the scalar fallback. This works even if Level::Fallback is not compiled in, always returning false in that case. (#168[] by [@​valadaptive][])
• Added store_array methods to store SIMD vectors back to memory explicitly using intrinsics. (#181[] by [@​LaurenzV][])

Fixed

• Improved the performance for load/store operations of vectors. (#185[] by [@​valadaptive][])
• Integer equality comparisons now function properly on x86. Previously, they performed "greater than" comparisons. (#115[] by [@​valadaptive][])
• All float-to-integer and integer-to-float conversions are implemented properly on x86, including the precise versions. (#134[] by [@​valadaptive][])
• The floating-point min_precise and max_precise operations now behave the same way on x86 and WebAssembly as they do on AArch64, returning the non-NaN operand if one operand is NaN and the other is not. Previously, they returned the second operand if either was NaN. (#136[] by [@​valadaptive][])

Changed

• Breaking change: The AVX2 level now requires all features from the x86-64-v3 baseline. (#188[] by [@​Shnatsel][])

• Breaking change: Level::fallback has been removed, replaced with Level::baseline. (#105[] by [@​DJMcNab][]) This corresponds with a change to avoid compiling in support for the fallback level on compilation targets which don't require it; this is most impactful for binary size on WASM, Apple Silicon Macs or Android. A consequence of this is that the available variants on Level are now dependent on the target features you are compiling with. The fallback level can be restored with the force_support_fallback cargo feature. We don't expect this to be necessary outside of tests.

• Code generation for select and unzip operations on x86 has been improved. (#115[] by [@​valadaptive][])

• Breaking change: The native-width associated types (f32s, u8s, etc.) for the Avx2 struct have been widened from 128-bit types (like f32x4) to 256-bit types (like f32x8). (#123[] by [@​valadaptive][])

• Breaking change: All the vector types' inherent methods have been removed. Any remaining functionality has been moved to trait methods. (#149[] by [@​valadaptive][])

  Some functionality is exposed under different names:

  • Instead of the reinterpret methods, use the bitcast method on the Bytes trait. (e.g. foo.reinterpret_i32() -> foo.bitcast::<i32x4<_>>())

... (truncated)

Changelog

Sourced from fearless_simd's changelog.

[0.4.0][] (2026-02-13)

This release has an [MSRV][] of 1.88.

Added

• All vector types now implement Index and IndexMut. (#112[] by [@​Ralith][])
• 256-bit vector types now use native AVX2 intrinsics on supported platforms. (#115[] by [@​valadaptive][])
• 8-bit integer multiplication is now implemented on x86. (#115[] by [@​valadaptive][])
• New native-width associated types: f64s and mask64s. (#125[] by [@​valadaptive][])
• The bitwise "not" operation on integer vector types. (#130[] by [@​valadaptive][])
• The from_fn method on vector types. (#137[] by [@​valadaptive][])
• The load_interleaved and store_interleaved operations now use native intrinsics on x86, instead of using the fallback implementations. (#140[] by [@​valadaptive][])
• Add support for relaxed_simd operations in WebAssembly. (#143[] by [@​valadaptive][])
• The ceil and round_ties_even operations on floating-point vector types. (Rust's round operation rounds away from zero in the case of ties. Many architectures do not natively implement that behavior, so it's omitted.) (#145[] by [@​valadaptive][])
• A prelude module, which exports all the traits in the library but not the types. (#149[] by [@​valadaptive][])
• The any_true, all_true, any_false, and all_false methods on mask types. (#141[] by [@​valadaptive][])
• Documentation for most traits, vector types, and operations. (#154[] by [@​valadaptive][])
• A "shift left by vector" operation, to go with the existing "shift right by vector". (#155[] by [@​valadaptive][])
• "Precise" float-to-integer conversions, which saturate out-of-bounds results and convert NaN to 0 across all platforms. (#167[] by [@​valadaptive][])
• Add the slide and slide_within_blocks methods for shifting elements within a vector. (#164[] by [@​valadaptive][])
• The Level::is_fallback method, which lets you check if the current SIMD level is the scalar fallback. This works even if Level::Fallback is not compiled in, always returning false in that case. (#168[] by [@​valadaptive][])
• Added store_array methods to store SIMD vectors back to memory explicitly using intrinsics. (#181[] by [@​LaurenzV][])

Fixed

• Improved the performance for load/store operations of vectors. (#185[] by [@​valadaptive][])
• Integer equality comparisons now function properly on x86. Previously, they performed "greater than" comparisons. (#115[] by [@​valadaptive][])
• All float-to-integer and integer-to-float conversions are implemented properly on x86, including the precise versions. (#134[] by [@​valadaptive][])
• The floating-point min_precise and max_precise operations now behave the same way on x86 and WebAssembly as they do on AArch64, returning the non-NaN operand if one operand is NaN and the other is not. Previously, they returned the second operand if either was NaN. (#136[] by [@​valadaptive][])

Changed

• Breaking change: The AVX2 level now requires all features from the x86-64-v3 baseline. (#188[] by [@​Shnatsel][])

• Breaking change: Level::fallback has been removed, replaced with Level::baseline. (#105[] by [@​DJMcNab][]) This corresponds with a change to avoid compiling in support for the fallback level on compilation targets which don't require it; this is most impactful for binary size on WASM, Apple Silicon Macs or Android. A consequence of this is that the available variants on Level are now dependent on the target features you are compiling with. The fallback level can be restored with the force_support_fallback cargo feature. We don't expect this to be necessary outside of tests.

• Code generation for select and unzip operations on x86 has been improved. (#115[] by [@​valadaptive][])

• Breaking change: The native-width associated types (f32s, u8s, etc.) for the Avx2 struct have been widened from 128-bit types (like f32x4) to 256-bit types (like f32x8). (#123[] by [@​valadaptive][])

• Breaking change: All the vector types' inherent methods have been removed. Any remaining functionality has been moved to trait methods. (#149[] by [@​valadaptive][])

  Some functionality is exposed under different names:

  • Instead of the reinterpret methods, use the bitcast method on the Bytes trait. (e.g. foo.reinterpret_i32() -> foo.bitcast::<i32x4<_>>())
  • Instead of the cvt methods, use the to_int or to_float convenience methods on the SimdFloat and SimdInt

... (truncated)

Commits

• c3632ab Prepare v0.4.0 release (#200)
• 05f68a4 Less overzealous inlining (#183)
• ba3ddfa Fix Aarch64 QEMU CI job (#199)
• f9ff199 Better test coverage for 256-bit and 512-bit vectors (#192)
• 56da100 Add Aarch64 QEMU job to CI (#198)
• 264ec78 Run CI tests in Intel SDE with all feature levels (#197)
• d930caf Run tests under Address Sanitizer on CI (#193)
• dfda2a8 Use x86-64-v3 architecture features for AVX2 level (#188)
• bbb430b Add a "slide" operation (like x86's alignr and ARM's vext) (#164)
• 280cc28 Bump lint set to v8 (#191)
• Additional commits viewable in compare view

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[dependabot]

Looks like fearless_simd is up-to-date now, so this is no longer needed.