[AMDGPU] comgr: split non-stride64 DS 2-address ops for A0#2281
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Follow-up to llvm#2369. The split-aware wait bump was incrementing drains (s_wait_dscnt 0) along with bounded waits, relaxing them and letting split halves escape into a downstream data hazard. Skip the bump when imm == 0; non-drain waits still bump by +1. Signed-off-by: xintin <gaurav.verma@amd.com>
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…ore test hotswap-trampoline-ds-nostride64.s: add ds_store_2addr_b64 kernel exercising fmtRegOperand on b64 data pairs. Signed-off-by: xintin <gaurav.verma@amd.com>
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Follow-up to #2369. The split-aware wait bump was incrementing drains (s_wait_dscnt 0) along with bounded waits, relaxing them and letting split halves escape into a downstream data hazard. Skip the bump when imm == 0; non-drain waits still bump by +1. This will unlock PR #2281. (follow-up #2585): a small dataflow pass at the wait site computing the bump from `(outstanding-count-at-wait, K)`. It would subsume the drain special-case naturally and remove the `// TODO:` marker left in `bumpNextWaitDscnt`. --------- Signed-off-by: xintin <gaurav.verma@amd.com>
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Signed-off-by: xintin <gaurav.verma@amd.com>
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Depends on #2584.
Summary
A0 silicon requires DS 2-address instructions to have offsets aligned to the payload size.
B0 dropped that restriction, so a B0-compiled binary may emit a 2-address DS instruction with unaligned offsets that silently corrupts LDS on A0.
The trampoline PR (introduced in #2369, with the drain-preserving wait fix in #2584) already covers the stride64 variants. This PR extends
getDs2AddrReplacementandextractDsOperandsincomgr-hotswap-patch-trampoline.cppto the non-stride64 encodings of the same families, including thestorexchgform:ds_load_2addr_b32ds_load_b32index * 4ds_load_2addr_b64ds_load_b64index * 8ds_store_2addr_b32ds_store_b32index * 4ds_store_2addr_b64ds_store_b64index * 8ds_storexchg_2addr_rtn_b32ds_storexchg_rtn_b32index * 4ds_storexchg_2addr_rtn_b64ds_storexchg_rtn_b64index * 8The stride64 forms encode
index * 64 * ElemBytesbyte offsets; the non-stride64 forms encodeindex * ElemBytes. Replacement single-address instructions take byte offsets directly, so a single ternary inextractDsOperandsmaterialises the right scale for each encoding and the layout-specific expansion helpers are unchanged.Follow-up
LLVMStateat init time (same follow-up as #2257).