feat(ame): add AME support to DiffTest - #909
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yu-yake2002
marked this pull request as draft
July 12, 2026 13:11
…mework - Introduces AmuCtrl event handling, including new classes and methods for event recording, queuing, and validation. - Add support for CSRs in AME.
- Check mrelease in amuctrl event. - Temporarily disable DEBUG_REFILL.
- Implement TokenEvent. - Enable the check on msyncreset & macquire.
- Update global mem at matrix store. - Enable Refill Check.
- AmuCtrlRecorder/AmuCtrlChecker - AmuExecRecorder/AmuExecChecker - TokenRecorder/TokenChecker
- Move existing CPU MMA verification logic into CpuMmaBackend. - Add IMmaBackend abstraction and wire MmaVerifier through backend->verify(). - Add CUDA backend stub, gateway config flag, and CUDA toolchain detection.
- Restore CUDA MMA backend host/kernel implementation - Align CPU and CUDA MMA accumulation with CUTE reduce-width K chunking - Fix integer MMA signedness decode in CPU/CUDA backend selection - Build CUDA kernel object only when DIFFTEST_CONFIG enables CUDA backend - Pass DIFFTEST_CONFIG into difftest sub-make targets - Add CUDA include/lib path fallback for system CUDA installations
Place mma_backend_cuda_kernel.o before -lcudart in SIM_LDFLAGS so the Verilator emulator links CUDA runtime symbols correctly.
Print whether the MMA reference model uses the CPU or CUDA backend when matrix difftest verification is initialized.
Share a host/device CUTE reduction model for FP32 and INT32 MMA so CPU and CUDA verification follow the same fixed-width K-chunk accumulation. Restrict the current verifier to 32-bit result types, add TF32 dispatch, track the shared CUDA model headers, rename the backend interface, and report the selected reference backend through difftest logging.
Remove mlsqIdx and isMls from the common instruction commit bundle. Neither field is consumed by the difftest runtime, while both extend the generated interface for configurations without matrix support.
yu-yake2002
marked this pull request as ready for review
July 17, 2026 10:33
- replace DiffTest error-path polling with an explicit flush - wait for queued and in-flight MMA checks to complete - retain the first mismatch while draining later requests - simplify worker stop and restart synchronization
Flush and stop all MMA verifier workers before LightSSS creates a checkpoint so child processes do not inherit stale thread handles. Restart the workers in the parent, in awakened checkpoint children, and after fork failures.
Group MMA verification under a dedicated directory and move CPU/CUDA implementations into mma/backend. Update include and CUDA build paths without changing behavior.
Move CPU/CUDA backend selection out of GatewayConfig and into the Make configuration. Default to the CPU backend, validate supported values, enable CUDA flags only for MMA_BACKEND=cuda, and document the new software-side interface.
klin02
approved these changes
Jul 21, 2026
Lemover
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Jul 28, 2026
- Add DiffTest interfaces for: - Matrix CSRs - AMU control and execution-finish events - Matrix store events - Matrix synchronization events - Track matrix instructions in a software ROB and synchronize their control, execution, and commit states between DUT and REF. - Support matrix load/store, matrix arithmetic, MMA, `mzero`, `mrelease`, `msyncregreset`, `macquire`, `mfence`, and asynchronous matrix instructions. - Add matrix store checking and update GoldenMem for refill checking. - Add asynchronous MMA result verification with a CPU/CUDA backend. - Support configurable matrix dimensions, bank layouts, and per-bank write masks.
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Background
XSAI integrates the AI Matrix Extension (AME). This PR adds DiffTest support for AME, allowing matrix instructions and state changes to be checked against the reference model.
Changes
mzero,mrelease,msyncregreset,macquire,mfence, and asynchronous matrix instructions.