Implementation of Zvbc extension - #209
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* The definitions of uops are independent with source data type. * vmerge_vv uop will be used by vmerge.vvm, vmv.v.v * vmerge_vx uop will be used by vmerge.v[xi]m, vmv.v.[xi], vfmv.v.f, vfmerge.vfm. * vmvnr uop will be used by vmv[1248]r.v. * vmv_x2vs uop will be used by vmv.s.x and vfmv.s.f. * vmv_vs2x uop will be use by vmv.x.s and vfmv.f.s.
* The definitions of uops are independent with source data type. * vmerge_vv uop will be used by vmerge.vvm, vmv.v.v * vmerge_vx uop will be used by vmerge.v[xi]m, vmv.v.[xi], vfmv.v.f, vfmerge.vfm. * vmvnr uop will be used by vmv[1248]r.v. * vmv_x2vs uop will be used by vmv.s.x and vfmv.s.f. * vmv_vs2x uop will be use by vmv.x.s and vfmv.f.s.
* The VectorAgnosticMergeUnit is used to handle agnostic merging of end of each vector UOP.
* Vector v2
* Add encode for VIALU.
* Refactor VFixPoint64b, VIntAdder64b.
* Add common class Module IntRoundInc to produce round increment.
* Handle eew select outside.
* Add VectorIntBitOp64b and VectorIntShift64b.
* Merge two SewOH class in object Common.
* Add name arg in splitToVec method in VecUIntUtil. * Add rev8 method in UIntUtil. + The rev8 will split UInt into several 8bit numbers, then reverse all numbers and cat them
* VSha256c(vsha2c[lh].vv, EEW=32), VSha512c(vsha2c[lh].vv, EEW=64) and VSm3c(vsm3c.vi) are connected to CryptoIterationCtrl constitute CryptoIteration. + VSha256c is a 2-stage module, each round result a~h will be stored in regs in CryptoIterationCtrl. + VSha512c is a 4-stage module, each round result a~h and tmp result t1 and t2 will also be stored in CryptoIterationCtrl. + VSm3c is a 4-stage module, each round result h~a and tmp result GGj + w0 + h, FFj + x0 + d, ss1 and ss2 will be stored in CryptoIterationCtrl. * VSha256ms(vsha2ms, EEW=32) use iteration methods, since its all 128b*3 source data can be acquired at once. * VSha512ms(vsha2ms, EEW=64) will be split into 4 uops when LMUL=2. VSha512ms fuse sig0 and sig1 two uops. These two uop use the same adder2 and adder3.
* Support fmax, fmin, fmaxm, fminm, fsgnj, fsgnjx, fsgnjn * Support FCMP in yunsuan difftest
* Support fmax, fmin, fmaxm, fminm, fsgnj, fsgnjx, fsgnjn * Support FCMP in yunsuan difftest
refactor(decode): scalar decode uop split
… VxsatWen trait FixPoint unconditionally outputs vxsatAdder as vxsat, causing vminu/vmin/vmaxu/vmax to incorrectly set vxsat. * Add needVxsat control to FixPoint.InCtrl to gate out.res.vxsat, precisely excluding both max/min and vwadd4u/vwadd4. * Gate out.res.narrowVxsat with isNClip * Add VxsatWen trait to vssubu/vssub opcodes
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