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feat(TestTop): support for L2 Power Down #77

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6c38299
feat(TestTop): support for L2 Power Down
Kumonda221-CrO3 Apr 3, 2026
896511f
submodule(CoupledL2): bump CoupledL2
Kumonda221-CrO3 Apr 3, 2026
5c55d5a
feat(TestTop): add link down port
Kumonda221-CrO3 Apr 3, 2026
8f21a3a
feat(TestTop): support Seperate Reset
Kumonda221-CrO3 Apr 7, 2026
a1eef7b
feat(TestTop): CHI channel probes
Kumonda221-CrO3 Apr 23, 2026
949b453
chore(TestTop): tweaked sizes of CoupledL2 and OpenLLC
Kumonda221-CrO3 Apr 23, 2026
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2 changes: 1 addition & 1 deletion coupledL2
Open in desktop
Submodule coupledL2 updated 33 files
+22 −2 .github/workflows/main.yml
+1 −1 .mill-version
+19 −12 build.sc
+7 −3 src/main/scala/coupledL2/BaseSlice.scala
+43 −2 src/main/scala/coupledL2/Common.scala
+12 −16 src/main/scala/coupledL2/CoupledL2.scala
+2 −1 src/main/scala/coupledL2/DataStorage.scala
+8 −5 src/main/scala/coupledL2/L2Param.scala
+19 −6 src/main/scala/coupledL2/RequestBuffer.scala
+90 −189 src/main/scala/coupledL2/TopDownMonitor.scala
+16 −5 src/main/scala/coupledL2/prefetch/BestOffsetPrefetch.scala
+2 −0 src/main/scala/coupledL2/prefetch/PrefetchParameters.scala
+43 −28 src/main/scala/coupledL2/prefetch/Prefetcher.scala
+0 −31 src/main/scala/coupledL2/tl2chi/Bundle.scala
+10 −11 src/main/scala/coupledL2/tl2chi/MMIOBridge.scala
+14 −12 src/main/scala/coupledL2/tl2chi/MSHR.scala
+9 −4 src/main/scala/coupledL2/tl2chi/MSHRCtl.scala
+13 −5 src/main/scala/coupledL2/tl2chi/MainPipe.scala
+0 −1 src/main/scala/coupledL2/tl2chi/RXDAT.scala
+3 −7 src/main/scala/coupledL2/tl2chi/RXSNP.scala
+7 −3 src/main/scala/coupledL2/tl2chi/Slice.scala
+22 −15 src/main/scala/coupledL2/tl2chi/TL2CHICoupledL2.scala
+8 −7 src/main/scala/coupledL2/tl2chi/TXDAT.scala
+110 −12 src/main/scala/coupledL2/tl2chi/chi/AsyncBridge.scala
+19 −11 src/main/scala/coupledL2/tl2chi/chi/LinkLayer.scala
+13 −5 src/main/scala/coupledL2/tl2chi/chi/Opcode.scala
+0 −35 src/main/scala/coupledL2/tl2tl/Bundle.scala
+7 −0 src/main/scala/coupledL2/tl2tl/MSHR.scala
+10 −4 src/main/scala/coupledL2/tl2tl/MSHRCtl.scala
+6 −0 src/main/scala/coupledL2/tl2tl/MainPipe.scala
+7 −4 src/main/scala/coupledL2/tl2tl/Slice.scala
+26 −13 src/main/scala/coupledL2/utils/GatedSplittedSRAM.scala
+1 −1 utility
62 changes: 57 additions & 5 deletions src/test/scala/TestTop.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -199,6 +199,31 @@ class TestTopSoC(numCores: Int = 1, numULAgents: Int = 0, banks: Int = 1, issue:
val l2Hint = Valid(new L2ToL1Hint)
}))

val io_powerdown = IO(Vec(numCores, new Bundle {
val flushAll = Input(Bool())
val flushAllDone = Output(Bool())
val cpuHalt = Input(Bool())
}))

val io_probe_chi = IO(Vec(numCores, new Bundle {
val txreq_flit = Output(UInt((new CHIREQ).getWidth.W))
val txrsp_flit = Output(UInt((new CHIRSP).getWidth.W))
val txdat_flit = Output(UInt((new CHIDAT).getWidth.W))
val rxsnp_flit = Output(UInt((new CHISNP).getWidth.W))
val rxrsp_flit = Output(UInt((new CHIRSP).getWidth.W))
val rxdat_flit = Output(UInt((new CHIDAT).getWidth.W))
val txreq_flitv = Output(Bool())
val txrsp_flitv = Output(Bool())
val txdat_flitv = Output(Bool())
val rxsnp_flitv = Output(Bool())
val rxrsp_flitv = Output(Bool())
val rxdat_flitv = Output(Bool())
}))

val io_linkdown = IO(Vec(numCores, Output(Bool())))

val io_resetsep = IO(Vec(numCores, Input(Bool())))

val cycle = RegInit(0.U(64.W))
cycle := cycle + 1.U

Expand Down Expand Up @@ -232,7 +257,7 @@ class TestTopSoC(numCores: Int = 1, numULAgents: Int = 0, banks: Int = 1, issue:
val l3 = Module(new OpenLLC()(new Config((site, here, up) => {
case CHIIssue => issue
case OpenLLCParamKey => l3Params.copy(
clientCaches = Seq.fill(numCores)(l2Params.copy(ways = 2, sets = 2)),
clientCaches = Seq.fill(numCores)(l2Params.copy(ways = 4, sets = 16)),
fullAddressBits = ADDR_WIDTH,
hartIds = 0 until numCores
)
Expand All @@ -251,6 +276,20 @@ class TestTopSoC(numCores: Int = 1, numULAgents: Int = 0, banks: Int = 1, issue:

l2_nodes.zipWithIndex.foreach { case (l2, i) =>

io_probe_chi(i).txreq_flit := l2.module.io_chi.tx.req.flit
io_probe_chi(i).txrsp_flit := l2.module.io_chi.tx.rsp.flit
io_probe_chi(i).txdat_flit := l2.module.io_chi.tx.dat.flit
io_probe_chi(i).rxsnp_flit := l2.module.io_chi.rx.snp.flit
io_probe_chi(i).rxrsp_flit := l2.module.io_chi.rx.rsp.flit
io_probe_chi(i).rxdat_flit := l2.module.io_chi.rx.dat.flit

io_probe_chi(i).txreq_flitv := l2.module.io_chi.tx.req.flitv
io_probe_chi(i).txrsp_flitv := l2.module.io_chi.tx.rsp.flitv
io_probe_chi(i).txdat_flitv := l2.module.io_chi.tx.dat.flitv
io_probe_chi(i).rxsnp_flitv := l2.module.io_chi.rx.snp.flitv
io_probe_chi(i).rxrsp_flitv := l2.module.io_chi.rx.rsp.flitv
io_probe_chi(i).rxdat_flitv := l2.module.io_chi.rx.dat.flitv

if (!l3Params.FPGAPlatform && l3Params.enableCHILog) {
CLogB.logFlitsRNOfRNF(
id = clogIdUpstream,
Expand All @@ -272,12 +311,22 @@ class TestTopSoC(numCores: Int = 1, numULAgents: Int = 0, banks: Int = 1, issue:
dontTouch(l2.module.io)

l2.module.io.l2_hint <> io_l1(i).l2Hint

l2.module.io.l2Flush.foreach(_ := io_powerdown(i).flushAll)
io_powerdown(i).flushAllDone := l2.module.io.l2FlushDone.getOrElse(false.B)
l2.module.io_cpu_halt.foreach(_ := io_powerdown(i).cpuHalt)

l2.module.io.hartId := i.U
l2.module.io.pfCtrlFromCore := DontCare
l2.module.io_nodeID := i.U(NODEID_WIDTH.W)
l2.module.io.debugTopDown := DontCare
l2.module.io.l2_tlb_req <> DontCare

l2.module.reset := io_resetsep(i) || reset.asBool

io_linkdown(i) := !l2.module.io_chi.syscoreq && !l2.module.io_chi.syscoack &&
!l2.module.io_chi.tx.linkactivereq && !l2.module.io_chi.tx.linkactiveack &&
!l2.module.io_chi.rx.linkactivereq && !l2.module.io_chi.rx.linkactiveack
}

if (!l3Params.FPGAPlatform && l3Params.enableCHILog) {
Expand Down Expand Up @@ -340,7 +389,7 @@ object TestTopSoCHelper {
val config = new Config((_, _, _) => {
case L2ParamKey => L2Param(
ways = 4,
sets = 128,
sets = 16,
clientCaches = Seq(L1Param(aliasBitsOpt = Some(2))),
// echoField = Seq(DirtyField),
enablePerf = enablePerf,
Expand All @@ -355,11 +404,14 @@ object TestTopSoCHelper {
dataCheck = Some("oddparity"),

// SAM for tester ICN: Home Node ID = 33
sam = Seq(AddressSet.everything -> 33)
sam = Seq(AddressSet.everything -> 33),

// L2 flush all
enableL2Flush = true
)
case OpenLLCParamKey => OpenLLCParam(
ways = 2,
sets = 2,
ways = 4,
sets = 32,
banks = 1,
clientCaches = Seq(L2Param()),
enablePerf = enablePerf,
Expand Down
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