fix(RVH): ignore MXR for implicit G-stage reads

[fuhuakai]

VS page-table memory accesses are implicit G-stage reads, and the RISC-V manual limits MXR to explicit memory accesses, so remove the MXR fallback from gpa_stage for VS page-table walks.

[github-actions]

NEMU Performance Results - XS Interpreter

Test	Guest Instructions	Host Instructions	Estimated Host Throughput (instr/s)	Actual NEMU Throughput (instr/s)	Baseline Host Instructions	Baseline Actual NEMU Throughput (instr/s)	Change vs Baseline (Instructions)	Change vs Baseline (Throughput)
bitmanip.bin	1.385e+05	5.199e+07	2.664e+07	3.132e+07	5.199e+07	2.739e+07	-0.00%	+14.33%
coremark-riscv64-xs-rv64gc-o2.bin	3.354e+06	1.752e+08	1.914e+08	1.748e+08	1.752e+08	1.804e+08	+0.00%	-3.10%
coremark-riscv64-xs-rv64gc-o3.bin	3.394e+06	1.747e+08	1.943e+08	1.865e+08	1.747e+08	1.810e+08	+0.00%	+3.04%
coremark-riscv64-xs-rv64gcb-o3.bin	3.035e+06	1.718e+08	1.766e+08	1.686e+08	1.718e+08	1.748e+08	+0.00%	-3.57%
amtest-riscv64-xs.bin	1.587e+04	8.708e+06	1.823e+07	1.616e+07	8.706e+06	1.878e+07	-0.02%	-13.95%
aliastest-riscv64-xs.bin	1.376e+03	7.711e+06	1.785e+06	3.163e+06	7.708e+06	6.521e+06	-0.03%	-51.49%
softprefetchtest-riscv64-xs.bin	2.643e+03	7.756e+06	3.408e+06	5.721e+06	7.757e+06	5.449e+06	+0.00%	+4.98%
zacas-riscv64-xs.bin	6.470e+04	1.222e+07	5.294e+07	2.033e+07	1.222e+07	1.720e+07	+0.00%	+18.23%
linux-hello	6.677e+07	1.676e+10	3.984e+07	4.912e+07	1.676e+10	4.862e+07	+0.00%	+1.03%

NEMU Performance Results - XS Ref Shared Object

Test	Guest Instructions	Host Instructions	Estimated Host Throughput (instr/s)	Actual NEMU Throughput (instr/s)	Baseline Host Instructions	Baseline Actual NEMU Throughput (instr/s)	Change vs Baseline (Instructions)	Change vs Baseline (Throughput)
bitmanip.bin	1.385e+05	1.094e+09	1.266e+06	7.420e+05	1.094e+09	6.925e+05	-0.00%	+7.14%
coremark-riscv64-xs-rv64gc-o2.bin	3.354e+06	6.387e+09	5.252e+06	3.300e+06	6.387e+09	3.217e+06	+0.00%	+2.55%
coremark-riscv64-xs-rv64gc-o3.bin	3.394e+06	6.415e+09	5.291e+06	3.237e+06	6.415e+09	4.462e+06	+0.00%	-27.46%
coremark-riscv64-xs-rv64gcb-o3.bin	3.035e+06	6.036e+09	5.028e+06	3.105e+06	6.036e+09	3.063e+06	+0.00%	+1.37%
amtest-riscv64-xs.bin	1.588e+04	3.435e+07	4.621e+06	2.156e+06	3.435e+07	1.815e+06	-0.00%	+18.78%
aliastest-riscv64-xs.bin	1.379e+03	4.850e+06	2.843e+06	7.670e+05	4.850e+06	7.734e+05	+0.00%	-0.83%
softprefetchtest-riscv64-xs.bin	2.646e+03	6.938e+06	3.814e+06	1.166e+06	6.938e+06	1.244e+06	-0.00%	-6.30%
zacas-riscv64-xs.bin	6.471e+04	1.288e+08	5.024e+06	1.692e+06	1.288e+08	1.994e+06	-0.00%	-15.14%
linux-hello	7.522e+07	6.673e+11	1.127e+06	1.074e+06	6.673e+11	1.037e+06	+0.00%	+3.53%

• Host Instructions is measured by DynamoRIO's inscount client.
• Estimated Host Throughput assumes a fixed 4GHz CPU and IPC=2.5.
• Actual NEMU Throughput is a single native NEMU run and may vary with host CPU performance.
• Baseline columns are populated on pull_request runs when the PR base contains the same defconfig.
• Change vs Baseline (Instructions) is computed from host instruction count; positive means fewer host instructions than baseline.
• Change vs Baseline (Throughput) is computed from native throughput; positive means faster than baseline.