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feat(mpt): add mpt v0.4 support to NEMU#1046

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HaoyuanLiuHZPH wants to merge 7 commits into
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HaoyuanLiuHZPH:feat_mpt_check
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feat(mpt): add mpt v0.4 support to NEMU#1046
HaoyuanLiuHZPH wants to merge 7 commits into
OpenXiangShan:masterfrom
HaoyuanLiuHZPH:feat_mpt_check

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@HaoyuanLiuHZPH

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Related issue: N/A

Type of change: feature request, other enhancement

Impact: add new MPT extension

Development Phase: implementation

Release Notes

This PR adds MPT v0.4 functionality into the NEMU. Memory Protection Tables (MPT) is a RISC-V hardware extension that enforces fine‑grained access control on physical memory. It is designed for multi‑tenant and multi‑supervisor‑domain environments, where traditional isolation mechanisms (PMP, MMU) are insufficient. MPT allows a root domain security manager (RDSM) to define per‑domain access policies (read, write, execute) for arbitrary physical memory regions, using a multi‑level table structure stored in memory. It works alongside PMP and the virtual memory system: an access is allowed only if all three protection mechanisms permit it.

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NEMU Performance Results - XS Interpreter

Test Guest Instructions Host Instructions Estimated Host Throughput (instr/s) Actual NEMU Throughput (instr/s) Baseline Host Instructions Baseline Actual NEMU Throughput (instr/s) Change vs Baseline (Instructions) Change vs Baseline (Throughput)
bitmanip.bin 1.385e+05 5.148e+07 2.691e+07 3.314e+07 5.148e+07 2.977e+07 -0.01% +11.34%
coremark-riscv64-xs-rv64gc-o2.bin 3.354e+06 1.731e+08 1.937e+08 1.880e+08 1.731e+08 1.916e+08 +0.00% -1.91%
coremark-riscv64-xs-rv64gc-o3.bin 3.394e+06 1.726e+08 1.967e+08 1.874e+08 1.726e+08 1.921e+08 -0.00% -2.48%
coremark-riscv64-xs-rv64gcb-o3.bin 3.035e+06 1.698e+08 1.788e+08 1.777e+08 1.698e+08 1.776e+08 -0.00% +0.09%
amtest-riscv64-xs.bin 1.587e+04 8.692e+06 1.826e+07 1.731e+07 8.690e+06 2.061e+07 -0.03% -16.03%
aliastest-riscv64-xs.bin 1.376e+03 7.702e+06 1.787e+06 3.004e+06 7.702e+06 4.327e+06 +0.00% -30.57%
softprefetchtest-riscv64-xs.bin 2.643e+03 7.752e+06 3.409e+06 4.457e+06 7.750e+06 5.860e+06 -0.03% -23.95%
zacas-riscv64-xs.bin 6.470e+04 1.218e+07 5.313e+07 1.992e+07 1.218e+07 1.885e+07 -0.02% +5.67%
linux-hello 7.545e+07 1.855e+10 4.068e+07 4.933e+07 1.855e+10 4.946e+07 -0.00% -0.27%

NEMU Performance Results - XS Ref Shared Object

Test Guest Instructions Host Instructions Estimated Host Throughput (instr/s) Actual NEMU Throughput (instr/s) Baseline Host Instructions Baseline Actual NEMU Throughput (instr/s) Change vs Baseline (Instructions) Change vs Baseline (Throughput)
bitmanip.bin 1.385e+05 1.129e+09 1.227e+06 6.946e+05 1.129e+09 6.838e+05 +0.00% +1.58%
coremark-riscv64-xs-rv64gc-o2.bin 3.354e+06 7.053e+09 4.756e+06 3.717e+06 7.053e+09 2.977e+06 -0.00% +24.83%
coremark-riscv64-xs-rv64gc-o3.bin 3.394e+06 7.088e+09 4.789e+06 3.023e+06 7.088e+09 2.999e+06 +0.00% +0.78%
coremark-riscv64-xs-rv64gcb-o3.bin 3.035e+06 6.640e+09 4.570e+06 2.934e+06 6.640e+09 2.846e+06 +0.00% +3.07%
amtest-riscv64-xs.bin 1.588e+04 3.916e+07 4.054e+06 1.596e+06 3.916e+07 1.741e+06 +0.00% -8.31%
aliastest-riscv64-xs.bin 1.379e+03 6.802e+06 2.027e+06 5.741e+05 6.802e+06 6.024e+05 +0.01% -4.70%
softprefetchtest-riscv64-xs.bin 2.646e+03 9.138e+06 2.896e+06 9.430e+05 9.139e+06 9.689e+05 +0.01% -2.67%
zacas-riscv64-xs.bin 6.471e+04 1.432e+08 4.519e+06 1.797e+06 1.432e+08 1.832e+06 +0.00% -1.93%
linux-hello 7.522e+07 6.921e+11 1.087e+06 9.722e+05 6.921e+11 1.017e+06 -0.00% -4.41%
  • Host Instructions is measured by DynamoRIO's inscount client.
  • Estimated Host Throughput assumes a fixed 4GHz CPU and IPC=2.5.
  • Actual NEMU Throughput is a single native NEMU run and may vary with host CPU performance.
  • Baseline columns are populated on pull_request runs when the PR base contains the same defconfig.
  • Change vs Baseline (Instructions) is computed from host instruction count; positive means fewer host instructions than baseline.
  • Change vs Baseline (Throughput) is computed from native throughput; positive means faster than baseline.

@good-circle
good-circle requested review from Lemover and fuhuakai June 30, 2026 03:03
@Lemover

Lemover commented Jun 30, 2026

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Good job, LGTM.

Comment thread src/memory/paddr.c
return false;
}

#ifdef CONFIG_RV_MPT_CHECK

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This wires the MPT permission check only into check_paddr(). However, with
CONFIG_PERF_OPT, normal translated accesses use the Host TLB path in vaddr.c. A
Host TLB miss will call paddr_read() / paddr_write() and therefore check MPT
once, but after the entry is filled, hosttlb_read() / hosttlb_write() hit paths
directly use host_read() / host_write() without calling check_paddr() again.

This means the cached Host TLB entry is not coherent with MPT state. In particular,
regarding invalidating Host TLB entries: the current CSR side effect only flushes on
satp writes.

Please confirm whether the issue described above actually exists. Should we make Host
TLB entries coherent with the MPT state? I am concerned that the current
implementation carries significant risk, so please evaluate and fix it.

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the TLB now flushes when mmpt csr changes.

Comment thread src/cpu/cpu-exec.c Outdated
cpu.mbmc = reg_ss.mbmc;
#endif
#ifdef CONFIG_RV_MPT_CHECK
reg_ss.mmpt = cpu.mmpt;

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Do you mean "cpu.mmpt = reg_ss.mmpt;" here? Seem to be opposite.

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fixed

Comment thread src/memory/paddr.c Outdated
Comment on lines +262 to +264
raise_read_access_fault(trap_type, vaddr);
Log("isa mpt check failed, vaddr=" FMT_WORD ", paddr=" FMT_PADDR ", len=0x%x, type=0x%x, mode=0x%x",
vaddr, addr, len, type, mode);

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Here should first "Log" and then "raise_access_fault". Because if we raise a fault first, the execution flow will jump away and will not come back to execute the log output here.

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fixed

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github-actions Bot commented Jul 9, 2026

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NEMU Performance Results - XS Interpreter

Test Guest Instructions Host Instructions Estimated Host Throughput (instr/s) Actual NEMU Throughput (instr/s) Baseline Host Instructions Baseline Actual NEMU Throughput (instr/s) Change vs Baseline (Instructions)
bitmanip.bin 1.385e+05 5.742e+07 2.412e+07 2.842e+07 5.742e+07 1.508e+07 +0.00%
coremark-riscv64-xs-rv64gc-o2.bin 3.354e+06 1.946e+08 1.723e+08 1.891e+08 1.946e+08 2.002e+08 +0.00%
coremark-riscv64-xs-rv64gc-o3.bin 3.394e+06 1.940e+08 1.750e+08 1.481e+08 1.940e+08 2.110e+08 +0.00%
coremark-riscv64-xs-rv64gcb-o3.bin 3.035e+06 1.911e+08 1.588e+08 1.892e+08 1.911e+08 1.964e+08 +0.00%
amtest-riscv64-xs.bin 1.587e+04 8.830e+06 1.798e+07 2.192e+07 8.830e+06 1.804e+07 -0.00%
aliastest-riscv64-xs.bin 1.376e+03 7.734e+06 1.779e+06 3.833e+06 7.734e+06 4.132e+06 +0.00%
softprefetchtest-riscv64-xs.bin 2.643e+03 7.787e+06 3.394e+06 5.758e+06 7.787e+06 5.847e+06 -0.00%
zacas-riscv64-xs.bin 6.470e+04 1.266e+07 5.110e+07 2.102e+07 1.266e+07 2.035e+07 +0.00%
rvv-workload-suite 4.566e+04 1.111e+08 4.110e+06 4.654e+06 1.111e+08 5.893e+06 +0.00%
linux-hello 6.677e+07 1.688e+10 3.955e+07 4.805e+07 1.688e+10 4.804e+07 -0.00%

NEMU Performance Results - XS Ref Shared Object

Test Guest Instructions Host Instructions Estimated Host Throughput (instr/s) Actual NEMU Throughput (instr/s) Baseline Host Instructions Baseline Actual NEMU Throughput (instr/s) Change vs Baseline (Instructions)
bitmanip.bin 1.385e+05 1.097e+09 1.262e+06 1.375e+06 1.097e+09 1.388e+06 +0.00%
coremark-riscv64-xs-rv64gc-o2.bin 3.354e+06 6.447e+09 5.203e+06 4.995e+06 6.447e+09 4.951e+06 -0.00%
coremark-riscv64-xs-rv64gc-o3.bin 3.394e+06 6.475e+09 5.242e+06 5.168e+06 6.475e+09 5.148e+06 -0.00%
coremark-riscv64-xs-rv64gcb-o3.bin 3.035e+06 6.090e+09 4.983e+06 4.879e+06 6.090e+09 4.997e+06 +0.00%
amtest-riscv64-xs.bin 1.588e+04 3.464e+07 4.583e+06 2.112e+06 3.464e+07 1.848e+06 +0.00%
aliastest-riscv64-xs.bin 1.379e+03 4.878e+06 2.827e+06 6.370e+05 4.878e+06 5.673e+05 -0.00%
softprefetchtest-riscv64-xs.bin 2.646e+03 6.989e+06 3.786e+06 1.347e+06 6.989e+06 8.494e+05 +0.00%
zacas-riscv64-xs.bin 6.471e+04 1.300e+08 4.979e+06 2.128e+06 1.300e+08 2.220e+06 -0.00%
rvv-workload-suite 4.568e+04 4.311e+08 1.060e+06 7.592e+05 4.311e+08 6.214e+05 -0.00%
linux-hello 7.522e+07 6.683e+11 1.125e+06 1.279e+06 6.683e+11 1.232e+06 +0.00%
  • Host Instructions is measured by DynamoRIO's inscount client.
  • Estimated Host Throughput assumes a fixed 4GHz CPU and IPC=2.5.
  • Actual NEMU Throughput is a single native NEMU run and may vary with host CPU performance.
  • Baseline columns are populated on pull_request runs when the PR base contains the same defconfig.
  • Change vs Baseline (Instructions) is computed from host instruction count; positive means fewer host instructions than baseline.

@fuhuakai

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lgtm

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3 participants