XS-GEM5 version: xs-dev
NEMU version: gcpt_new_mem_layout
nexus-am version: master
test without difftest:
`root@9a24524da7f2:/workspace/GEM5# ./build/RISCV/gem5.opt ./configs/example/kmh.py --raw-cpt --generic-rv-cpt=../nexus-am/apps/rvv-trigger/build/r
riscv64-xs/ rvv-trigger-riscv64-xs.bin rvv-trigger-riscv64-xs.elf rvv-trigger-riscv64-xs.txt
root@9a24524da7f2:/workspace/GEM5# ./build/RISCV/gem5.opt ./configs/example/kmh.py --raw-cpt --generic-rv-cpt=../nexus
-am/apps/rvv-trigger/build/rvv-trigger-riscv64-xs.bin
gem5 Simulator System. https://www.gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 version [DEVELOP-FOR-22.1]
gem5 compiled Apr 22 2025 09:54:38
gem5 started Apr 28 2025 08:54:08
gem5 executing on 9a24524da7f2, pid 18880
command line: ./build/RISCV/gem5.opt ./configs/example/kmh.py --raw-cpt --generic-rv-cpt=../nexus-am/apps/rvv-trigger/build/rvv-trigger-riscv64-xs.bin
[<m5.params.AddrRange object at 0x7f49f8959db0>]
gcpt_restorer is None
Simulating single core without RVV, demanding GCPT restorer size of 0x700.
Using raw bbl ../nexus-am/apps/rvv-trigger/build/rvv-trigger-riscv64-xs.bin
Attach 1 decoders to thread with addr: .cpu.decoder
Create threads for test sys cpu (XiangshanCore)
create_prefetcher at l2: L2CompositeWithWorkerPrefetcher
create_prefetcher at l3: WorkerPrefetcher
create_prefetcher at l1i: None
create_prefetcher at l1d: XSCompositePrefetcher
Finish memory system configuration
No switch cpu_class provided
Global frequency set at 1000000000000 ticks per second
warn: No dot file generated. Please install pydot to generate the dot file and pdf.
build/RISCV/arch/riscv/bare_metal/fs_workload.cc:60: info: No bootload provided, because using XS GCPT, reset to 0x80000000
build/RISCV/cpu/o3/issue_queue.cc:166: warn: load0: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:166: warn: load1: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:166: warn: load2: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:166: warn: store0: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:166: warn: store1: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:166: warn: std0: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:166: warn: std1: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:166: warn: fpIQ2: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:166: warn: vecIQ0: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdAes
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdAesMix
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdSha1Hash
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdSha1Hash2
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdSha256Hash
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdSha256Hash2
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdShaSigma2
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdShaSigma3
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdPredAlu
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: IprAccess
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: InstPrefetch
build/RISCV/cpu/base.cc:240: warn: Difftest is disabled
build/RISCV/cpu/o3/cpu.cc:236: warn: Setting isa ptr of cpu to 0x559aa17d6c60
build/RISCV/base/statistics.hh:281: warn: One of the stats is a legacy stat. Legacy stat is a stat that does not belong to any statistics::Group. Legacy stat is deprecated.
0: system.remote_gdb: listening for remote gdb on port 7000
Registering probe listeners for BaseO3CPU system.cpu
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher
system.cpu.dcache.prefetcher addTLB system.cpu.mmu.dtb
system.cpu.dcache.prefetcher addHintDownStream system.l2_caches.prefetcher
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.berti
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.bop_large
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.bop_learned
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.bop_small
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.cmc
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.ipcp
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.opt
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.spp
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.sstride
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.xsstream
Registering probe listeners for Prefetcher system.l2_caches.prefetcher
system.l2_caches.prefetcher addTLB system.cpu.mmu.dtb
system.l2_caches.prefetcher addHintDownStream system.l3.prefetcher
Registering probe listeners for Prefetcher system.l2_caches.prefetcher.bop_large
Registering probe listeners for Prefetcher system.l2_caches.prefetcher.bop_small
Registering probe listeners for Prefetcher system.l2_caches.prefetcher.cdp
Registering probe listeners for Prefetcher system.l2_caches.prefetcher.cmc
Registering probe listeners for Prefetcher system.l3.prefetcher
build/RISCV/mem/physical.cc:507: warn: Unserializing physical memory from file ../nexus-am/apps/rvv-trigger/build/rvv-trigger-riscv64-xs.bin
build/RISCV/mem/physical.cc:578: info: copying ../nexus-am/apps/rvv-trigger/build/rvv-trigger-riscv64-xs.bin to pmem 0x7f47f8678000
build/RISCV/mem/physical.cc:608: info: First 4 bytes are 0x93 0x0 0x0 0x0
build/RISCV/sim/system.cc:561: info: Restored from Xiangshan RISC-V Checkpoint
**** REAL SIMULATION ****
build/RISCV/sim/simulate.cc:194: info: Entering event queue @ 0. Starting simulation...
build/RISCV/dev/serial/uartlite.cc:35: warn: Write to other uartlite addr 12 is not implemented
----------test vle----------
test1: PASS: mcause: 0, vl: 8, vstart: 0
test2: FAIL: mcause: 0, vl: 8, vstart: 0
test3: FAIL: mcause: 0, vl: 8, vstart: 0
test4: FAIL: mcause: 0, vl: 8, vstart: 0
test5: PASS: mcause: 0, vl: 8, vstart: 0
test6: PASS: mcause: 0, vl: 8, vstart: 0
----------test vlm----------
test1: PASS: mcause: 0, vl: 8, vstart: 0
test2: FAIL: mcause: 0, vl: 8, vstart: 0
test3: FAIL: mcause: 0, vl: 16, vstart: 0
test4: FAIL: mcause: 0, vl: 12, vstart: 0
----------test vlse----------
test1: PASS: mcause: 0, vl: 8, vstart: 0
test2: FAIL: mcause: 0, vl: 8, vstart: 0
test3: FAIL: mcause: 0, vl: 8, vstart: 0
test4: FAIL: mcause: 0, vl: 8, vstart: 0
test5: PASS: mcause: 0, vl: 8, vstart: 0
test6: PASS: mcause: 0, vl: 8, vstart: 0
----------test vlxe----------
test1: PASS: mcause: 0, vl: 8, vstart: 0
test1: FAIL: mcause: 0, vl: 8, vstart: 0
test3: FAIL: mcause: 0, vl: 8, vstart: 0
test4: PASS: mcause: 0, vl: 8, vstart: 0
test5: PASS: mcause: 0, vl: 8, vstart: 0
----------test vleff----------
test1: PASS: mcause: 0, vl: 16, vstart: 0
test2: FAIL: mcause: 0, vl: 16, vstart: 0
test3: FAIL: mcause: 0, vl: 16, vstart: 0
----------test vlseg----------
test1: PASS: mcause: 0, vl: 8, vstart: 0
test2: FAIL: mcause: 0, vl: 8, vstart: 0
test3: FAIL: mcause: 0, vl: 8, vstart: 0
test4: FAIL: mcause: 0, vl: 8, vstart: 0
----------test vlsegff----------
test1: PASS: mcause: 0, vl: 8, vstart: 0
test2: FAIL: mcause: 0, vl: 8, vstart: 0
test3: FAIL: mcause: 0, vl: 8, vstart: 0
test4: FAIL: mcause: 0, vl: 8, vstart: 0
test5: FAIL: mcause: 0, vl: 8, vstart: 0
----------test vlsseg----------
test1: PASS: mcause: 0, vl: 8, vstart: 0
test2: FAIL: mcause: 0, vl: 8, vstart: 0
test3: FAIL: mcause: 0, vl: 8, vstart: 0
test4: FAIL: mcause: 0, vl: 8, vstart: 0
----------test vlxseg----------
test1: PASS: mcause: 0, vl: 8, vstart: 0
test2: FAIL: mcause: 0, vl: 8, vstart: 0
test3: FAIL: mcause: 0, vl: 8, vstart: 0
test4: FAIL: mcause: 0, vl: 8, vstart: 0
----------test vlr----------
test1: PASS: mcause: 0, vl: 8, vstart: 0
test2: FAIL: mcause: 0, vl: 8, vstart: 0
test3: FAIL: mcause: 0, vl: 8, vstart: 0
----------test vse----------
test1: PASS: mcause: 0, vl: 8, vstart: 0
test2: FAIL: mcause: 0, vl: 8, vstart: 0
test3: FAIL: mcause: 0, vl: 8, vstart: 0
test4: FAIL: mcause: 0, vl: 8, vstart: 0
test5: PASS: mcause: 0, vl: 8, vstart: 0
test6: PASS: mcause: 0, vl: 8, vstart: 0
----------test vsm----------
test1: PASS: mcause: 0, vl: 8, vstart: 0
test2: FAIL: mcause: 0, vl: 8, vstart: 0
test3: FAIL: mcause: 0, vl: 16, vstart: 0
test4: FAIL: mcause: 0, vl: 14, vstart: 0
----------test vsse----------
test1: PASS: mcause: 0, vl: 8, vstart: 0
test2: FAIL: mcause: 0, vl: 8, vstart: 0
test3: FAIL: mcause: 0, vl: 8, vstart: 0
test4: FAIL: mcause: 0, vl: 8, vstart: 0
test5: PASS: mcause: 0, vl: 8, vstart: 0
test6: PASS: mcause: 0, vl: 8, vstart: 0
----------test vsxe----------
test1: PASS: mcause: 0, vl: 8, vstart: 0
test2: FAIL: mcause: 0, vl: 8, vstart: 0
test3: FAIL: mcause: 0, vl: 8, vstart: 0
test4: PASS: mcause: 0, vl: 8, vstart: 0
test5: PASS: mcause: 0, vl: 8, vstart: 0
----------test vsseg----------
test1: PASS: mcause: 0, vl: 8, vstart: 0
test2: FAIL: mcause: 0, vl: 8, vstart: 0
test3: FAIL: mcause: 0, vl: 8, vstart: 0
test4: FAIL: mcause: 0, vl: 8, vstart: 0
----------test vssseg----------
test1: PASS: mcause: 0, vl: 8, vstart: 0
test2: FAIL: mcause: 0, vl: 8, vstart: 0
test3: FAIL: mcause: 0, vl: 8, vstart: 0
test4: FAIL: mcause: 0, vl: 8, vstart: 0
----------test vsxseg----------
test1: PASS: mcause: 0, vl: 8, vstart: 0
test2: FAIL: mcause: 0, vl: 8, vstart: 0
test3: FAIL: mcause: 0, vl: 8, vstart: 0
test4: FAIL: mcause: 0, vl: 8, vstart: 0
----------test vsr----------
test1: PASS: mcause: 0, vl: 8, vstart: 0
test2: FAIL: mcause: 0, vl: 8, vstart: 0
test3: FAIL: mcause: 0, vl: 8, vstart: 0
Exiting @ tick 2493697806 because m5_exit instruction encountered when simulating XS`
test with difftest:
`root@9a24524da7f2:/workspace/GEM5# ./build/RISCV/gem5.opt ./configs/example/kmh.py --raw-cpt --generic-rv-cpt=../nexus-am/apps/rvv-trigger/build/rvv-trigger-riscv64-xs.bin
gem5 Simulator System. https://www.gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 version [DEVELOP-FOR-22.1]
gem5 compiled Apr 22 2025 09:54:38
gem5 started Apr 28 2025 08:55:56
gem5 executing on 9a24524da7f2, pid 18881
command line: ./build/RISCV/gem5.opt ./configs/example/kmh.py --raw-cpt --generic-rv-cpt=../nexus-am/apps/rvv-trigger/build/rvv-trigger-riscv64-xs.bin
[<m5.params.AddrRange object at 0x7ffa054f5db0>]
Obtained ref_so from GCBV_REF_SO: /workspace/NEMU/build/riscv64-nemu-interpreter-so
gcpt_restorer is None
Simulating single core without RVV, demanding GCPT restorer size of 0x700.
Using raw bbl ../nexus-am/apps/rvv-trigger/build/rvv-trigger-riscv64-xs.bin
Attach 1 decoders to thread with addr: .cpu.decoder
Create threads for test sys cpu (XiangshanCore)
create_prefetcher at l2: L2CompositeWithWorkerPrefetcher
create_prefetcher at l3: WorkerPrefetcher
create_prefetcher at l1i: None
create_prefetcher at l1d: XSCompositePrefetcher
Finish memory system configuration
No switch cpu_class provided
Global frequency set at 1000000000000 ticks per second
warn: No dot file generated. Please install pydot to generate the dot file and pdf.
build/RISCV/arch/riscv/bare_metal/fs_workload.cc:60: info: No bootload provided, because using XS GCPT, reset to 0x80000000
build/RISCV/cpu/o3/issue_queue.cc:166: warn: load0: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:166: warn: load1: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:166: warn: load2: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:166: warn: store0: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:166: warn: store1: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:166: warn: std0: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:166: warn: std1: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:166: warn: fpIQ2: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:166: warn: vecIQ0: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdAes
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdAesMix
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdSha1Hash
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdSha1Hash2
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdSha256Hash
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdSha256Hash2
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdShaSigma2
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdShaSigma3
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdPredAlu
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: IprAccess
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: InstPrefetch
build/RISCV/cpu/base.cc:214: warn: cpu_id set to 0
Using /workspace/NEMU/build/riscv64-nemu-interpreter-so for difftest
build/RISCV/cpu/base.cc:228: warn: Difftest is enabled with ref so: /workspace/NEMU/build/riscv64-nemu-interpreter-so.
build/RISCV/cpu/o3/cpu.cc:236: warn: Setting isa ptr of cpu to 0x55fd3dcdcc60
build/RISCV/base/statistics.hh:281: warn: One of the stats is a legacy stat. Legacy stat is a stat that does not belong to any statistics::Group. Legacy stat is deprecated.
0: system.remote_gdb: listening for remote gdb on port 7000
Registering probe listeners for BaseO3CPU system.cpu
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher
system.cpu.dcache.prefetcher addTLB system.cpu.mmu.dtb
system.cpu.dcache.prefetcher addHintDownStream system.l2_caches.prefetcher
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.berti
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.bop_large
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.bop_learned
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.bop_small
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.cmc
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.ipcp
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.opt
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.spp
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.sstride
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.xsstream
Registering probe listeners for Prefetcher system.l2_caches.prefetcher
system.l2_caches.prefetcher addTLB system.cpu.mmu.dtb
system.l2_caches.prefetcher addHintDownStream system.l3.prefetcher
Registering probe listeners for Prefetcher system.l2_caches.prefetcher.bop_large
Registering probe listeners for Prefetcher system.l2_caches.prefetcher.bop_small
Registering probe listeners for Prefetcher system.l2_caches.prefetcher.cdp
Registering probe listeners for Prefetcher system.l2_caches.prefetcher.cmc
Registering probe listeners for Prefetcher system.l3.prefetcher
build/RISCV/mem/physical.cc:507: warn: Unserializing physical memory from file ../nexus-am/apps/rvv-trigger/build/rvv-trigger-riscv64-xs.bin
build/RISCV/mem/physical.cc:578: info: copying ../nexus-am/apps/rvv-trigger/build/rvv-trigger-riscv64-xs.bin to pmem 0x7ff7fcb0c000
build/RISCV/mem/physical.cc:608: info: First 4 bytes are 0x93 0x0 0x0 0x0
build/RISCV/sim/system.cc:561: info: Restored from Xiangshan RISC-V Checkpoint
**** REAL SIMULATION ****
build/RISCV/sim/simulate.cc:194: info: Entering event queue @ 0. Starting simulation...
build/RISCV/cpu/base.cc:1459: warn: Start memcpy to NEMU from 0x7ff7fcb0c000, size=8589934592
build/RISCV/cpu/base.cc:1462: warn: Start regcpy to NEMU
build/RISCV/cpu/base.hh:712: warn: In CPU0: NEMU PC: 0x80000000, GEM5 PC: 0x80000000, inst: mv ra, zero, 0
$0: 0x0000000000000000 ra: 0x0000000000000000 sp: 0x0000000000000000 gp: 0x0000000000000000
tp: 0x0000000000000000 t0: 0x0000000000000000 t1: 0x0000000000000000 t2: 0x0000000000000000
s0: 0x0000000000000000 s1: 0x0000000000000000 a0: 0x0000000000000000 a1: 0x0000000000000000
a2: 0x0000000000000000 a3: 0x0000000000000000 a4: 0x0000000000000000 a5: 0x0000000000000000
a6: 0x0000000000000000 a7: 0x0000000000000000 s2: 0x0000000000000000 s3: 0x0000000000000000
s4: 0x0000000000000000 s5: 0x0000000000000000 s6: 0x0000000000000000 s7: 0x0000000000000000
s8: 0x0000000000000000 s9: 0x0000000000000000 s10: 0x0000000000000000 s11: 0x0000000000000000
t3: 0x0000000000000000 t4: 0x0000000000000000 t5: 0x0000000000000000 t6: 0x0000000000000000
ft0: 0x0000000000000000 ft1: 0x0000000000000000 ft2: 0x0000000000000000 ft3: 0x0000000000000000
ft4: 0x0000000000000000 ft5: 0x0000000000000000 ft6: 0x0000000000000000 ft7: 0x0000000000000000
fs0: 0x0000000000000000 fs1: 0x0000000000000000 fa0: 0x0000000000000000 fa1: 0x0000000000000000
fa2: 0x0000000000000000 fa3: 0x0000000000000000 fa4: 0x0000000000000000 fa5: 0x0000000000000000
fa6: 0x0000000000000000 fa7: 0x0000000000000000 fs2: 0x0000000000000000 fs3: 0x0000000000000000
fs4: 0x0000000000000000 fs5: 0x0000000000000000 fs6: 0x0000000000000000 fs7: 0x0000000000000000
fs8: 0x0000000000000000 fs9: 0x0000000000000000 fs10: 0x0000000000000000 fs11: 0x0000000000000000
ft8: 0x0000000000000000 ft9: 0x0000000000000000 ft10: 0x0000000000000000 ft11: 0x0000000000000000
pc: 0x0000000080000004 mstatus: 0x0000000a00000000 mcause: 0x0000000000000000 mepc: 0x0000000000000000
sstatus: 0x0000000200000000 scause: 0x0000000000000000 sepc: 0x0000000000000000
satp: 0x0000000000000000
mip: 0x0000000000000000 mie: 0x0000000000000000 mscratch: 0x0000000000000000 sscratch: 0x0000000000000000
mideleg: 0x0000000000000000 medeleg: 0x0000000000000000
mtval: 0x0000000000000000 stval: 0x0000000000000000 mtvec: 0x0000000000000000 stvec: 0x0000000000000000
privilege mode:3
pmp: 16 entries active, details:
0: cfg:0x00 addr:0x0000000000000000| 1: cfg:0x00 addr:0x0000000000000000
2: cfg:0x00 addr:0x0000000000000000| 3: cfg:0x00 addr:0x0000000000000000
4: cfg:0x00 addr:0x0000000000000000| 5: cfg:0x00 addr:0x0000000000000000
6: cfg:0x00 addr:0x0000000000000000| 7: cfg:0x00 addr:0x0000000000000000
8: cfg:0x00 addr:0x0000000000000000| 9: cfg:0x00 addr:0x0000000000000000
10: cfg:0x00 addr:0x0000000000000000|11: cfg:0x00 addr:0x0000000000000000
12: cfg:0x00 addr:0x0000000000000000|13: cfg:0x00 addr:0x0000000000000000
14: cfg:0x00 addr:0x0000000000000000|15: cfg:0x00 addr:0x0000000000000000
v0 : 0x0000000000000000_0000000000000000 v1 : 0x0000000000000000_0000000000000000
v2 : 0x0000000000000000_0000000000000000 v3 : 0x0000000000000000_0000000000000000
v4 : 0x0000000000000000_0000000000000000 v5 : 0x0000000000000000_0000000000000000
v6 : 0x0000000000000000_0000000000000000 v7 : 0x0000000000000000_0000000000000000
v8 : 0x0000000000000000_0000000000000000 v9 : 0x0000000000000000_0000000000000000
v10: 0x0000000000000000_0000000000000000 v11: 0x0000000000000000_0000000000000000
v12: 0x0000000000000000_0000000000000000 v13: 0x0000000000000000_0000000000000000
v14: 0x0000000000000000_0000000000000000 v15: 0x0000000000000000_0000000000000000
v16: 0x0000000000000000_0000000000000000 v17: 0x0000000000000000_0000000000000000
v18: 0x0000000000000000_0000000000000000 v19: 0x0000000000000000_0000000000000000
v20: 0x0000000000000000_0000000000000000 v21: 0x0000000000000000_0000000000000000
v22: 0x0000000000000000_0000000000000000 v23: 0x0000000000000000_0000000000000000
v24: 0x0000000000000000_0000000000000000 v25: 0x0000000000000000_0000000000000000
v26: 0x0000000000000000_0000000000000000 v27: 0x0000000000000000_0000000000000000
v28: 0x0000000000000000_0000000000000000 v29: 0x0000000000000000_0000000000000000
v30: 0x0000000000000000_0000000000000000 v31: 0x0000000000000000_0000000000000000
vtype: 0x0000000000000000 vstart: 0x0000000000000000 vxsat: 0x0000000000000000
vxrm: 0x0000000000000000 vl: 0x0000000000000000 vcsr: 0x0000000000000000
build/RISCV/cpu/base.cc:1520: warn: gem5-rRegsDisplay :
$0 : 0 ra : 0 sp : 0 gp : 0
tp : 0 t0 : 0 t1 : 0 t2 : 0
s0 : 0 s1 : 0 a0 : 0 a1 : 0
a2 : 0 a3 : 0 a4 : 0 a5 : 0
a6 : 0 a7 : 0 s2 : 0 s3 : 0
s4 : 0 s5 : 0 s6 : 0 s7 : 0
s8 : 0 s9 : 0 s10 : 0 s11 : 0
t3 : 0 t4 : 0 t5 : 0 t6 : 0
build/RISCV/cpu/base.cc:1533: warn: gem5-fRegsDisplay :
ft0 : 0 ft1 : 0 ft2 : 0 ft3 : 0
ft4 : 0 ft5 : 0 ft6 : 0 ft7 : 0
fs0 : 0 fs1 : 0 fa0 : 0 fa1 : 0
fa2 : 0 fa3 : 0 fa4 : 0 fa5 : 0
fa6 : 0 fa7 : 0 fs2 : 0 fs3 : 0
fs4 : 0 fs5 : 0 fs6 : 0 fs7 : 0
fs8 : 0 fs9 : 0 fs10 : 0 fs11 : 0
ft8 : 0 ft9 : 0 ft10 : 0 ft11 : 0
build/RISCV/cpu/base.cc:1584: warn: gem5-CsrDisplay :
pc : 80000000 mstatus : a00000000 mcause : 0 mepc : 0
sstatus : 200000000 scause : 0 sepc : 0
satp : 0
mip : 0 mie : 0 mscratch: 0 sscratch: 0
mideleg : 0 medeleg : 0
mtval : 0 stval : 0 mtvec : 0 stvec : 0
privilege mode : 3
build/RISCV/cpu/base.cc:1609: warn: gem5-VectorDisplay :
v00 : 0000000000000000_0000000000000000 v01 : 0000000000000000_0000000000000000
v02 : 0000000000000000_0000000000000000 v03 : 0000000000000000_0000000000000000
v04 : 0000000000000000_0000000000000000 v05 : 0000000000000000_0000000000000000
v06 : 0000000000000000_0000000000000000 v07 : 0000000000000000_0000000000000000
v08 : 0000000000000000_0000000000000000 v09 : 0000000000000000_0000000000000000
v10 : 0000000000000000_0000000000000000 v11 : 0000000000000000_0000000000000000
v12 : 0000000000000000_0000000000000000 v13 : 0000000000000000_0000000000000000
v14 : 0000000000000000_0000000000000000 v15 : 0000000000000000_0000000000000000
v16 : 0000000000000000_0000000000000000 v17 : 0000000000000000_0000000000000000
v18 : 0000000000000000_0000000000000000 v19 : 0000000000000000_0000000000000000
v20 : 0000000000000000_0000000000000000 v21 : 0000000000000000_0000000000000000
v22 : 0000000000000000_0000000000000000 v23 : 0000000000000000_0000000000000000
v24 : 0000000000000000_0000000000000000 v25 : 0000000000000000_0000000000000000
v26 : 0000000000000000_0000000000000000 v27 : 0000000000000000_0000000000000000
v28 : 0000000000000000_0000000000000000 v29 : 0000000000000000_0000000000000000
v30 : 0000000000000000_0000000000000000 v31 : 0000000000000000_0000000000000000
vtype : 8000000000000000 vstart : 0 vxsat : 0
vxrm : 0 vl : 0 vcsr : 0
build/RISCV/cpu/base.hh:715: warn: start dump last 1 committed msg
build/RISCV/cpu/base.hh:718: warn: V [sn:1 pc:0x80000000] mv ra, zero, 0
build/RISCV/cpu/base.cc:1487: panic: Difftest failed!
Memory Usage: 17140000 KBytes
Program aborted at tick 65601
Aborted (core dumped)`
XS-GEM5 version: xs-dev
NEMU version: gcpt_new_mem_layout
nexus-am version: master
test without difftest:
`root@9a24524da7f2:/workspace/GEM5# ./build/RISCV/gem5.opt ./configs/example/kmh.py --raw-cpt --generic-rv-cpt=../nexus-am/apps/rvv-trigger/build/r
riscv64-xs/ rvv-trigger-riscv64-xs.bin rvv-trigger-riscv64-xs.elf rvv-trigger-riscv64-xs.txt
root@9a24524da7f2:/workspace/GEM5# ./build/RISCV/gem5.opt ./configs/example/kmh.py --raw-cpt --generic-rv-cpt=../nexus
-am/apps/rvv-trigger/build/rvv-trigger-riscv64-xs.bin
gem5 Simulator System. https://www.gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 version [DEVELOP-FOR-22.1]
gem5 compiled Apr 22 2025 09:54:38
gem5 started Apr 28 2025 08:54:08
gem5 executing on 9a24524da7f2, pid 18880
command line: ./build/RISCV/gem5.opt ./configs/example/kmh.py --raw-cpt --generic-rv-cpt=../nexus-am/apps/rvv-trigger/build/rvv-trigger-riscv64-xs.bin
[<m5.params.AddrRange object at 0x7f49f8959db0>]
gcpt_restorer is None
Simulating single core without RVV, demanding GCPT restorer size of 0x700.
Using raw bbl ../nexus-am/apps/rvv-trigger/build/rvv-trigger-riscv64-xs.bin
Attach 1 decoders to thread with addr: .cpu.decoder
Create threads for test sys cpu (XiangshanCore)
create_prefetcher at l2: L2CompositeWithWorkerPrefetcher
create_prefetcher at l3: WorkerPrefetcher
create_prefetcher at l1i: None
create_prefetcher at l1d: XSCompositePrefetcher
Finish memory system configuration
No switch cpu_class provided
Global frequency set at 1000000000000 ticks per second
warn: No dot file generated. Please install pydot to generate the dot file and pdf.
build/RISCV/arch/riscv/bare_metal/fs_workload.cc:60: info: No bootload provided, because using XS GCPT, reset to 0x80000000
build/RISCV/cpu/o3/issue_queue.cc:166: warn: load0: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:166: warn: load1: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:166: warn: load2: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:166: warn: store0: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:166: warn: store1: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:166: warn: std0: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:166: warn: std1: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:166: warn: fpIQ2: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:166: warn: vecIQ0: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdAes
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdAesMix
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdSha1Hash
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdSha1Hash2
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdSha256Hash
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdSha256Hash2
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdShaSigma2
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdShaSigma3
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdPredAlu
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: IprAccess
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: InstPrefetch
build/RISCV/cpu/base.cc:240: warn: Difftest is disabled
build/RISCV/cpu/o3/cpu.cc:236: warn: Setting isa ptr of cpu to 0x559aa17d6c60
build/RISCV/base/statistics.hh:281: warn: One of the stats is a legacy stat. Legacy stat is a stat that does not belong to any statistics::Group. Legacy stat is deprecated.
0: system.remote_gdb: listening for remote gdb on port 7000
Registering probe listeners for BaseO3CPU system.cpu
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher
system.cpu.dcache.prefetcher addTLB system.cpu.mmu.dtb
system.cpu.dcache.prefetcher addHintDownStream system.l2_caches.prefetcher
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.berti
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.bop_large
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.bop_learned
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.bop_small
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.cmc
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.ipcp
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.opt
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.spp
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.sstride
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.xsstream
Registering probe listeners for Prefetcher system.l2_caches.prefetcher
system.l2_caches.prefetcher addTLB system.cpu.mmu.dtb
system.l2_caches.prefetcher addHintDownStream system.l3.prefetcher
Registering probe listeners for Prefetcher system.l2_caches.prefetcher.bop_large
Registering probe listeners for Prefetcher system.l2_caches.prefetcher.bop_small
Registering probe listeners for Prefetcher system.l2_caches.prefetcher.cdp
Registering probe listeners for Prefetcher system.l2_caches.prefetcher.cmc
Registering probe listeners for Prefetcher system.l3.prefetcher
build/RISCV/mem/physical.cc:507: warn: Unserializing physical memory from file ../nexus-am/apps/rvv-trigger/build/rvv-trigger-riscv64-xs.bin
build/RISCV/mem/physical.cc:578: info: copying ../nexus-am/apps/rvv-trigger/build/rvv-trigger-riscv64-xs.bin to pmem 0x7f47f8678000
build/RISCV/mem/physical.cc:608: info: First 4 bytes are 0x93 0x0 0x0 0x0
build/RISCV/sim/system.cc:561: info: Restored from Xiangshan RISC-V Checkpoint
**** REAL SIMULATION ****
build/RISCV/sim/simulate.cc:194: info: Entering event queue @ 0. Starting simulation...
build/RISCV/dev/serial/uartlite.cc:35: warn: Write to other uartlite addr 12 is not implemented
----------test vle----------
test1: PASS: mcause: 0, vl: 8, vstart: 0
test2: FAIL: mcause: 0, vl: 8, vstart: 0
test3: FAIL: mcause: 0, vl: 8, vstart: 0
test4: FAIL: mcause: 0, vl: 8, vstart: 0
test5: PASS: mcause: 0, vl: 8, vstart: 0
test6: PASS: mcause: 0, vl: 8, vstart: 0
----------test vlm----------
test1: PASS: mcause: 0, vl: 8, vstart: 0
test2: FAIL: mcause: 0, vl: 8, vstart: 0
test3: FAIL: mcause: 0, vl: 16, vstart: 0
test4: FAIL: mcause: 0, vl: 12, vstart: 0
----------test vlse----------
test1: PASS: mcause: 0, vl: 8, vstart: 0
test2: FAIL: mcause: 0, vl: 8, vstart: 0
test3: FAIL: mcause: 0, vl: 8, vstart: 0
test4: FAIL: mcause: 0, vl: 8, vstart: 0
test5: PASS: mcause: 0, vl: 8, vstart: 0
test6: PASS: mcause: 0, vl: 8, vstart: 0
----------test vlxe----------
test1: PASS: mcause: 0, vl: 8, vstart: 0
test1: FAIL: mcause: 0, vl: 8, vstart: 0
test3: FAIL: mcause: 0, vl: 8, vstart: 0
test4: PASS: mcause: 0, vl: 8, vstart: 0
test5: PASS: mcause: 0, vl: 8, vstart: 0
----------test vleff----------
test1: PASS: mcause: 0, vl: 16, vstart: 0
test2: FAIL: mcause: 0, vl: 16, vstart: 0
test3: FAIL: mcause: 0, vl: 16, vstart: 0
----------test vlseg----------
test1: PASS: mcause: 0, vl: 8, vstart: 0
test2: FAIL: mcause: 0, vl: 8, vstart: 0
test3: FAIL: mcause: 0, vl: 8, vstart: 0
test4: FAIL: mcause: 0, vl: 8, vstart: 0
----------test vlsegff----------
test1: PASS: mcause: 0, vl: 8, vstart: 0
test2: FAIL: mcause: 0, vl: 8, vstart: 0
test3: FAIL: mcause: 0, vl: 8, vstart: 0
test4: FAIL: mcause: 0, vl: 8, vstart: 0
test5: FAIL: mcause: 0, vl: 8, vstart: 0
----------test vlsseg----------
test1: PASS: mcause: 0, vl: 8, vstart: 0
test2: FAIL: mcause: 0, vl: 8, vstart: 0
test3: FAIL: mcause: 0, vl: 8, vstart: 0
test4: FAIL: mcause: 0, vl: 8, vstart: 0
----------test vlxseg----------
test1: PASS: mcause: 0, vl: 8, vstart: 0
test2: FAIL: mcause: 0, vl: 8, vstart: 0
test3: FAIL: mcause: 0, vl: 8, vstart: 0
test4: FAIL: mcause: 0, vl: 8, vstart: 0
----------test vlr----------
test1: PASS: mcause: 0, vl: 8, vstart: 0
test2: FAIL: mcause: 0, vl: 8, vstart: 0
test3: FAIL: mcause: 0, vl: 8, vstart: 0
----------test vse----------
test1: PASS: mcause: 0, vl: 8, vstart: 0
test2: FAIL: mcause: 0, vl: 8, vstart: 0
test3: FAIL: mcause: 0, vl: 8, vstart: 0
test4: FAIL: mcause: 0, vl: 8, vstart: 0
test5: PASS: mcause: 0, vl: 8, vstart: 0
test6: PASS: mcause: 0, vl: 8, vstart: 0
----------test vsm----------
test1: PASS: mcause: 0, vl: 8, vstart: 0
test2: FAIL: mcause: 0, vl: 8, vstart: 0
test3: FAIL: mcause: 0, vl: 16, vstart: 0
test4: FAIL: mcause: 0, vl: 14, vstart: 0
----------test vsse----------
test1: PASS: mcause: 0, vl: 8, vstart: 0
test2: FAIL: mcause: 0, vl: 8, vstart: 0
test3: FAIL: mcause: 0, vl: 8, vstart: 0
test4: FAIL: mcause: 0, vl: 8, vstart: 0
test5: PASS: mcause: 0, vl: 8, vstart: 0
test6: PASS: mcause: 0, vl: 8, vstart: 0
----------test vsxe----------
test1: PASS: mcause: 0, vl: 8, vstart: 0
test2: FAIL: mcause: 0, vl: 8, vstart: 0
test3: FAIL: mcause: 0, vl: 8, vstart: 0
test4: PASS: mcause: 0, vl: 8, vstart: 0
test5: PASS: mcause: 0, vl: 8, vstart: 0
----------test vsseg----------
test1: PASS: mcause: 0, vl: 8, vstart: 0
test2: FAIL: mcause: 0, vl: 8, vstart: 0
test3: FAIL: mcause: 0, vl: 8, vstart: 0
test4: FAIL: mcause: 0, vl: 8, vstart: 0
----------test vssseg----------
test1: PASS: mcause: 0, vl: 8, vstart: 0
test2: FAIL: mcause: 0, vl: 8, vstart: 0
test3: FAIL: mcause: 0, vl: 8, vstart: 0
test4: FAIL: mcause: 0, vl: 8, vstart: 0
----------test vsxseg----------
test1: PASS: mcause: 0, vl: 8, vstart: 0
test2: FAIL: mcause: 0, vl: 8, vstart: 0
test3: FAIL: mcause: 0, vl: 8, vstart: 0
test4: FAIL: mcause: 0, vl: 8, vstart: 0
----------test vsr----------
test1: PASS: mcause: 0, vl: 8, vstart: 0
test2: FAIL: mcause: 0, vl: 8, vstart: 0
test3: FAIL: mcause: 0, vl: 8, vstart: 0
Exiting @ tick 2493697806 because m5_exit instruction encountered when simulating XS`
test with difftest:
`root@9a24524da7f2:/workspace/GEM5# ./build/RISCV/gem5.opt ./configs/example/kmh.py --raw-cpt --generic-rv-cpt=../nexus-am/apps/rvv-trigger/build/rvv-trigger-riscv64-xs.bin
gem5 Simulator System. https://www.gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 version [DEVELOP-FOR-22.1]
gem5 compiled Apr 22 2025 09:54:38
gem5 started Apr 28 2025 08:55:56
gem5 executing on 9a24524da7f2, pid 18881
command line: ./build/RISCV/gem5.opt ./configs/example/kmh.py --raw-cpt --generic-rv-cpt=../nexus-am/apps/rvv-trigger/build/rvv-trigger-riscv64-xs.bin
[<m5.params.AddrRange object at 0x7ffa054f5db0>]
Obtained ref_so from GCBV_REF_SO: /workspace/NEMU/build/riscv64-nemu-interpreter-so
gcpt_restorer is None
Simulating single core without RVV, demanding GCPT restorer size of 0x700.
Using raw bbl ../nexus-am/apps/rvv-trigger/build/rvv-trigger-riscv64-xs.bin
Attach 1 decoders to thread with addr: .cpu.decoder
Create threads for test sys cpu (XiangshanCore)
create_prefetcher at l2: L2CompositeWithWorkerPrefetcher
create_prefetcher at l3: WorkerPrefetcher
create_prefetcher at l1i: None
create_prefetcher at l1d: XSCompositePrefetcher
Finish memory system configuration
No switch cpu_class provided
Global frequency set at 1000000000000 ticks per second
warn: No dot file generated. Please install pydot to generate the dot file and pdf.
build/RISCV/arch/riscv/bare_metal/fs_workload.cc:60: info: No bootload provided, because using XS GCPT, reset to 0x80000000
build/RISCV/cpu/o3/issue_queue.cc:166: warn: load0: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:166: warn: load1: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:166: warn: load2: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:166: warn: store0: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:166: warn: store1: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:166: warn: std0: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:166: warn: std1: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:166: warn: fpIQ2: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:166: warn: vecIQ0: Use one selector by multiple identical fus
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdAes
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdAesMix
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdSha1Hash
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdSha1Hash2
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdSha256Hash
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdSha256Hash2
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdShaSigma2
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdShaSigma3
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: SimdPredAlu
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: IprAccess
build/RISCV/cpu/o3/issue_queue.cc:726: warn: No config for opClass: InstPrefetch
build/RISCV/cpu/base.cc:214: warn: cpu_id set to 0
Using /workspace/NEMU/build/riscv64-nemu-interpreter-so for difftest
build/RISCV/cpu/base.cc:228: warn: Difftest is enabled with ref so: /workspace/NEMU/build/riscv64-nemu-interpreter-so.
build/RISCV/cpu/o3/cpu.cc:236: warn: Setting isa ptr of cpu to 0x55fd3dcdcc60
build/RISCV/base/statistics.hh:281: warn: One of the stats is a legacy stat. Legacy stat is a stat that does not belong to any statistics::Group. Legacy stat is deprecated.
0: system.remote_gdb: listening for remote gdb on port 7000
Registering probe listeners for BaseO3CPU system.cpu
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher
system.cpu.dcache.prefetcher addTLB system.cpu.mmu.dtb
system.cpu.dcache.prefetcher addHintDownStream system.l2_caches.prefetcher
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.berti
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.bop_large
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.bop_learned
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.bop_small
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.cmc
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.ipcp
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.opt
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.spp
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.sstride
Registering probe listeners for Prefetcher system.cpu.dcache.prefetcher.xsstream
Registering probe listeners for Prefetcher system.l2_caches.prefetcher
system.l2_caches.prefetcher addTLB system.cpu.mmu.dtb
system.l2_caches.prefetcher addHintDownStream system.l3.prefetcher
Registering probe listeners for Prefetcher system.l2_caches.prefetcher.bop_large
Registering probe listeners for Prefetcher system.l2_caches.prefetcher.bop_small
Registering probe listeners for Prefetcher system.l2_caches.prefetcher.cdp
Registering probe listeners for Prefetcher system.l2_caches.prefetcher.cmc
Registering probe listeners for Prefetcher system.l3.prefetcher
build/RISCV/mem/physical.cc:507: warn: Unserializing physical memory from file ../nexus-am/apps/rvv-trigger/build/rvv-trigger-riscv64-xs.bin
build/RISCV/mem/physical.cc:578: info: copying ../nexus-am/apps/rvv-trigger/build/rvv-trigger-riscv64-xs.bin to pmem 0x7ff7fcb0c000
build/RISCV/mem/physical.cc:608: info: First 4 bytes are 0x93 0x0 0x0 0x0
build/RISCV/sim/system.cc:561: info: Restored from Xiangshan RISC-V Checkpoint
**** REAL SIMULATION ****
build/RISCV/sim/simulate.cc:194: info: Entering event queue @ 0. Starting simulation...
build/RISCV/cpu/base.cc:1459: warn: Start memcpy to NEMU from 0x7ff7fcb0c000, size=8589934592
build/RISCV/cpu/base.cc:1462: warn: Start regcpy to NEMU
build/RISCV/cpu/base.hh:712: warn: In CPU0: NEMU PC: 0x80000000, GEM5 PC: 0x80000000, inst: mv ra, zero, 0
$0: 0x0000000000000000 ra: 0x0000000000000000 sp: 0x0000000000000000 gp: 0x0000000000000000
tp: 0x0000000000000000 t0: 0x0000000000000000 t1: 0x0000000000000000 t2: 0x0000000000000000
s0: 0x0000000000000000 s1: 0x0000000000000000 a0: 0x0000000000000000 a1: 0x0000000000000000
a2: 0x0000000000000000 a3: 0x0000000000000000 a4: 0x0000000000000000 a5: 0x0000000000000000
a6: 0x0000000000000000 a7: 0x0000000000000000 s2: 0x0000000000000000 s3: 0x0000000000000000
s4: 0x0000000000000000 s5: 0x0000000000000000 s6: 0x0000000000000000 s7: 0x0000000000000000
s8: 0x0000000000000000 s9: 0x0000000000000000 s10: 0x0000000000000000 s11: 0x0000000000000000
t3: 0x0000000000000000 t4: 0x0000000000000000 t5: 0x0000000000000000 t6: 0x0000000000000000
ft0: 0x0000000000000000 ft1: 0x0000000000000000 ft2: 0x0000000000000000 ft3: 0x0000000000000000
ft4: 0x0000000000000000 ft5: 0x0000000000000000 ft6: 0x0000000000000000 ft7: 0x0000000000000000
fs0: 0x0000000000000000 fs1: 0x0000000000000000 fa0: 0x0000000000000000 fa1: 0x0000000000000000
fa2: 0x0000000000000000 fa3: 0x0000000000000000 fa4: 0x0000000000000000 fa5: 0x0000000000000000
fa6: 0x0000000000000000 fa7: 0x0000000000000000 fs2: 0x0000000000000000 fs3: 0x0000000000000000
fs4: 0x0000000000000000 fs5: 0x0000000000000000 fs6: 0x0000000000000000 fs7: 0x0000000000000000
fs8: 0x0000000000000000 fs9: 0x0000000000000000 fs10: 0x0000000000000000 fs11: 0x0000000000000000
ft8: 0x0000000000000000 ft9: 0x0000000000000000 ft10: 0x0000000000000000 ft11: 0x0000000000000000
pc: 0x0000000080000004 mstatus: 0x0000000a00000000 mcause: 0x0000000000000000 mepc: 0x0000000000000000
sstatus: 0x0000000200000000 scause: 0x0000000000000000 sepc: 0x0000000000000000
satp: 0x0000000000000000
mip: 0x0000000000000000 mie: 0x0000000000000000 mscratch: 0x0000000000000000 sscratch: 0x0000000000000000
mideleg: 0x0000000000000000 medeleg: 0x0000000000000000
mtval: 0x0000000000000000 stval: 0x0000000000000000 mtvec: 0x0000000000000000 stvec: 0x0000000000000000
privilege mode:3
pmp: 16 entries active, details:
0: cfg:0x00 addr:0x0000000000000000| 1: cfg:0x00 addr:0x0000000000000000
2: cfg:0x00 addr:0x0000000000000000| 3: cfg:0x00 addr:0x0000000000000000
4: cfg:0x00 addr:0x0000000000000000| 5: cfg:0x00 addr:0x0000000000000000
6: cfg:0x00 addr:0x0000000000000000| 7: cfg:0x00 addr:0x0000000000000000
8: cfg:0x00 addr:0x0000000000000000| 9: cfg:0x00 addr:0x0000000000000000
10: cfg:0x00 addr:0x0000000000000000|11: cfg:0x00 addr:0x0000000000000000
12: cfg:0x00 addr:0x0000000000000000|13: cfg:0x00 addr:0x0000000000000000
14: cfg:0x00 addr:0x0000000000000000|15: cfg:0x00 addr:0x0000000000000000
v0 : 0x0000000000000000_0000000000000000 v1 : 0x0000000000000000_0000000000000000
v2 : 0x0000000000000000_0000000000000000 v3 : 0x0000000000000000_0000000000000000
v4 : 0x0000000000000000_0000000000000000 v5 : 0x0000000000000000_0000000000000000
v6 : 0x0000000000000000_0000000000000000 v7 : 0x0000000000000000_0000000000000000
v8 : 0x0000000000000000_0000000000000000 v9 : 0x0000000000000000_0000000000000000
v10: 0x0000000000000000_0000000000000000 v11: 0x0000000000000000_0000000000000000
v12: 0x0000000000000000_0000000000000000 v13: 0x0000000000000000_0000000000000000
v14: 0x0000000000000000_0000000000000000 v15: 0x0000000000000000_0000000000000000
v16: 0x0000000000000000_0000000000000000 v17: 0x0000000000000000_0000000000000000
v18: 0x0000000000000000_0000000000000000 v19: 0x0000000000000000_0000000000000000
v20: 0x0000000000000000_0000000000000000 v21: 0x0000000000000000_0000000000000000
v22: 0x0000000000000000_0000000000000000 v23: 0x0000000000000000_0000000000000000
v24: 0x0000000000000000_0000000000000000 v25: 0x0000000000000000_0000000000000000
v26: 0x0000000000000000_0000000000000000 v27: 0x0000000000000000_0000000000000000
v28: 0x0000000000000000_0000000000000000 v29: 0x0000000000000000_0000000000000000
v30: 0x0000000000000000_0000000000000000 v31: 0x0000000000000000_0000000000000000
vtype: 0x0000000000000000 vstart: 0x0000000000000000 vxsat: 0x0000000000000000
vxrm: 0x0000000000000000 vl: 0x0000000000000000 vcsr: 0x0000000000000000
build/RISCV/cpu/base.cc:1520: warn: gem5-rRegsDisplay :
$0 : 0 ra : 0 sp : 0 gp : 0
tp : 0 t0 : 0 t1 : 0 t2 : 0
s0 : 0 s1 : 0 a0 : 0 a1 : 0
a2 : 0 a3 : 0 a4 : 0 a5 : 0
a6 : 0 a7 : 0 s2 : 0 s3 : 0
s4 : 0 s5 : 0 s6 : 0 s7 : 0
s8 : 0 s9 : 0 s10 : 0 s11 : 0
t3 : 0 t4 : 0 t5 : 0 t6 : 0
build/RISCV/cpu/base.cc:1533: warn: gem5-fRegsDisplay :
ft0 : 0 ft1 : 0 ft2 : 0 ft3 : 0
ft4 : 0 ft5 : 0 ft6 : 0 ft7 : 0
fs0 : 0 fs1 : 0 fa0 : 0 fa1 : 0
fa2 : 0 fa3 : 0 fa4 : 0 fa5 : 0
fa6 : 0 fa7 : 0 fs2 : 0 fs3 : 0
fs4 : 0 fs5 : 0 fs6 : 0 fs7 : 0
fs8 : 0 fs9 : 0 fs10 : 0 fs11 : 0
ft8 : 0 ft9 : 0 ft10 : 0 ft11 : 0
build/RISCV/cpu/base.cc:1584: warn: gem5-CsrDisplay :
pc : 80000000 mstatus : a00000000 mcause : 0 mepc : 0
sstatus : 200000000 scause : 0 sepc : 0
satp : 0
mip : 0 mie : 0 mscratch: 0 sscratch: 0
mideleg : 0 medeleg : 0
mtval : 0 stval : 0 mtvec : 0 stvec : 0
privilege mode : 3
build/RISCV/cpu/base.cc:1609: warn: gem5-VectorDisplay :
v00 : 0000000000000000_0000000000000000 v01 : 0000000000000000_0000000000000000
v02 : 0000000000000000_0000000000000000 v03 : 0000000000000000_0000000000000000
v04 : 0000000000000000_0000000000000000 v05 : 0000000000000000_0000000000000000
v06 : 0000000000000000_0000000000000000 v07 : 0000000000000000_0000000000000000
v08 : 0000000000000000_0000000000000000 v09 : 0000000000000000_0000000000000000
v10 : 0000000000000000_0000000000000000 v11 : 0000000000000000_0000000000000000
v12 : 0000000000000000_0000000000000000 v13 : 0000000000000000_0000000000000000
v14 : 0000000000000000_0000000000000000 v15 : 0000000000000000_0000000000000000
v16 : 0000000000000000_0000000000000000 v17 : 0000000000000000_0000000000000000
v18 : 0000000000000000_0000000000000000 v19 : 0000000000000000_0000000000000000
v20 : 0000000000000000_0000000000000000 v21 : 0000000000000000_0000000000000000
v22 : 0000000000000000_0000000000000000 v23 : 0000000000000000_0000000000000000
v24 : 0000000000000000_0000000000000000 v25 : 0000000000000000_0000000000000000
v26 : 0000000000000000_0000000000000000 v27 : 0000000000000000_0000000000000000
v28 : 0000000000000000_0000000000000000 v29 : 0000000000000000_0000000000000000
v30 : 0000000000000000_0000000000000000 v31 : 0000000000000000_0000000000000000
vtype : 8000000000000000 vstart : 0 vxsat : 0
vxrm : 0 vl : 0 vcsr : 0
build/RISCV/cpu/base.hh:715: warn: start dump last 1 committed msg
build/RISCV/cpu/base.hh:718: warn: V [sn:1 pc:0x80000000] mv ra, zero, 0
build/RISCV/cpu/base.cc:1487: panic: Difftest failed!
Memory Usage: 17140000 KBytes
Program aborted at tick 65601
Aborted (core dumped)`