Pinned Loading

1. I2C-Master-ASIC-Implementation I2C-Master-ASIC-Implementation Public

   I2C Master ASIC flow is implemented using Synopsys tools. From RTL to GDS.

   Verilog 4

2. NMOS-PMOS-Fabrication-steps-in-sentaurus NMOS-PMOS-Fabrication-steps-in-sentaurus Public

   Using Sentaurus Sprocess module to simulate the steps of fabrication 90nm PMOS and NMOS transistors side by side.

   Batchfile 1

3. HLS-CNN-Acceleration HLS-CNN-Acceleration Public

   C++

4. Parallelized-3D-Poissons-Equation Parallelized-3D-Poissons-Equation Public

   C++

5. Scrambler-Verification- Scrambler-Verification- Public

   In this project, an encrypted Scrambler code is given and it is required to do verification using Systemverilog Testbench and a UVM testbench with given input vector and expected output.

   SystemVerilog

6. Simple-Airplane-landing-system Simple-Airplane-landing-system Public

   The project aims to design an embedded system that controls the airplane landing sequence using a Tiva C microcontroller, FreeRTOS as the real-time operating system the airplane's status.

   C