Openvaf-compiled model behaivor

[modestpe]

I have a simple memory device verilog-a model. Was able to compile and start to simulate.

variable "statei" was used to represent programmed state (= 1) or erased state (= 0) of the memory device.

When the memory device is in the programmed state, the resistance of the device becomes lower compared to the erased state.

The variable "statei" can transit to the target state with a programming pulse or an erasing pulse.

However, the variable "statei" reverts as soon as the programming pulse or erasing pulse is removed.

I have attached captured images and source codes to reproduce the error.

when we simulate the same code using Cadence verilog compiler and simulator. didn't observe this issue.

z2tps.zip

[Kreijstal]

This repo isn't mantained

[Lang0722]

Maybe a Hidden states issue.

[felix-salfelder]

The replies so far may be well intentioned, but fall short of an explanation what's going on.

OpenVAF works well with pure-analog aka. Spice compact device models, subject to the usual issues with Spice itself. The development here has basically stopped, but a few copies are maintained (elsewhere). Perhaps Kreijstal suggests to use a copy he is involved with.

The term "hidden state" was introduced to characterise requirements of closed source proprietary implementations. It is not clear how it can be used to describe the mishap in OpenVAF. OpenVAF is completely "open" as the name suggests and apparently states are not implemented at all. It is pretty clear what the standard requires, so this would need fixing.

Beyond states, hidden or not, in order to describe and simulate memory models (correctly), Verilog-A has significantly more on offer. Sensitivity to region changes should be modelled using cross events and output should be filtered, as the commented out "transition" line suggests. See LRM Section 5.10.3.1 for an explanation and for sample-and-hold examples much simpler than the memory model shown above.

[kev-cam]

For anyone interested in low-power digital design (DVFS), here's a modeling technique that works in Verilog-A - http://www.v-ms.com/ICCAD-2014.pdf Regards, Kev.

…

On Wed, Apr 9, 2025 at 8:39 AM felix ***@***.***> wrote: The replies so far may be well intentioned, but fall short of an explanation what's going on. OpenVAF works well with pure-analog aka. Spice compact device models, subject to the usual issues with Spice itself. The development here has basically stopped, but a few copies are maintained (elsewhere). Perhaps Kreijstal suggests to use a copy he is involved with. The term "hidden state" was introduced to characterise requirements of closed source proprietary implementations. It is not clear how it can be used to describe the mishap in OpenVAF. OpenVAF is completely "open" as the name suggests and apparently states are not implemented at all. It is pretty clear what the standard requires, so this would need fixing. Beyond states, hidden or not, in order to describe and simulate memory models (correctly), Verilog-A has significantly more on offer. Sensitivity to region changes should be modelled using cross events and output should be filtered, as the commented out "transition" line suggests. See LRM Section 5.10.3.1 for an explanation and for sample-and-hold examples much simpler than the memory model shown above. — Reply to this email directly, view it on GitHub <#157 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/ABPKEBDDPN4FEDNN5BRHVZL2YU5JLAVCNFSM6AAAAAB2P2WIPGVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDOOJQGE2DQNBRHE> . You are receiving this because you are subscribed to this thread.Message ID: ***@***.***> *felix-salfelder* left a comment (pascalkuthe/OpenVAF#157) <#157 (comment)> The replies so far may be well intentioned, but fall short of an explanation what's going on. OpenVAF works well with pure-analog aka. Spice compact device models, subject to the usual issues with Spice itself. The development here has basically stopped, but a few copies are maintained (elsewhere). Perhaps Kreijstal suggests to use a copy he is involved with. The term "hidden state" was introduced to characterise requirements of closed source proprietary implementations. It is not clear how it can be used to describe the mishap in OpenVAF. OpenVAF is completely "open" as the name suggests and apparently states are not implemented at all. It is pretty clear what the standard requires, so this would need fixing. Beyond states, hidden or not, in order to describe and simulate memory models (correctly), Verilog-A has significantly more on offer. Sensitivity to region changes should be modelled using cross events and output should be filtered, as the commented out "transition" line suggests. See LRM Section 5.10.3.1 for an explanation and for sample-and-hold examples much simpler than the memory model shown above. — Reply to this email directly, view it on GitHub <#157 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/ABPKEBDDPN4FEDNN5BRHVZL2YU5JLAVCNFSM6AAAAAB2P2WIPGVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDOOJQGE2DQNBRHE> . You are receiving this because you are subscribed to this thread.Message ID: ***@***.***>

[arpadbuermen]

Afaik in Verilog-A sometimes data is stored between iterations of the solver, like when transition() or slew() is used, because these functions need the value of the signal at some past timepoint. OpenVAF does not support transition(), so that is why your model is not working. I think you can also introduce hidden state by assigning a variable at certain events only, instead of at each model evaluation. In that case I think it retains its value between solver iterations. Such a variable represents a hidden state. Felix will know more because he extensively studied the standard.

Compact models of transistors are not supposed to rely on hidden states because if they do, then it is hard to formulate advanced analyses, like HB, since the model's response cannot be expressed as a solution of an ODE with excitation (model input) on its RHS.

Commercial simulators detect hidden state and prevent advanced analyses if such a model is used. There's a discussion on this subject somewhere on Cadence forums.

OpenVAF is intended for compact models and does not support hidden state in any way. A variable's value is never retained between model invocations. Judging from comments Pascal had plans to do this in the future. It is possible and would involve allocating a state in the simulator's state vector where the variable would be stored.

[wassawa1]

I may have hit an OpenVAF compiler panic while testing a very small Verilog-A model.

A simple fixed-output model like this:

analog begin
    V(pos) <+ 1.0;
    V(neg) <+ 2.0;
end

causes OpenVAF to abort during compilation:

thread '' panicked at 'called Option::unwrap() on a None value',
openvaf/mir_llvm/src/context.rs:80:42

This looks like an internal compiler panic rather than a normal Verilog-A diagnostic.

Here is a small testcase that reproduces the issue on my side.

`include "disciplines.vams"

module zcount(in, pos, neg);

    input in;
    output pos, neg;

    electrical in, pos, neg;

    parameter real vth   = 0.0;
    parameter real vhys  = 1m;
    parameter real start = 0.0;
    parameter real stop  = 120n;

    integer sumpos;
    integer sumneg;
    integer state;

    analog begin
        @(initial_step) begin
            sumpos = 0;
            sumneg = 0;
            state  = 0;
        end

        if (($abstime >= start) && ($abstime <= stop)) begin
            if ((state == 0) && (V(in) > vth + vhys)) begin
                sumpos = sumpos + 1;
                state  = 1;
            end

            if ((state == 1) && (V(in) < vth - vhys)) begin
                sumneg = sumneg + 1;
                state  = 0;
            end
        end

        V(pos) <+ sumpos;
        V(neg) <+ sumneg;
    end

endmodule

zcount_test.spice

• Minimal zero-cross counter test

VIN vin 0 SIN(0 1 50MEG)

.model zcmod zcount vth=0 vhys=1m start=0 stop=120n

N_ZC vin vpos vneg zcmod

.control
pre_osdi ./my_zcount.osdi
tran 0.1n 120n uic
set wr_singlescale
wrdata tran_result.txt v(vin) v(vpos) v(vneg)
quit
.endc

.end

Expected behavior:

v(vpos) should count rising zero crossings.
v(vneg) should count falling zero crossings.
For a 50 MHz sine wave over 120 ns, both should increase several times.

Observed behavior:

v(vin) is correct.
v(vpos) may briefly become 1 near the beginning, but the count is not retained as expected.
v(vneg) remains 0.

I also tested an even simpler fixed-output model:

`include "disciplines.vams"

module zcount(in, pos, neg);

    input in;
    output pos, neg;

    electrical in, pos, neg;

    analog begin
        V(pos) <+ 1.0;
        V(neg) <+ 2.0;
    end

endmodule

This causes OpenVAF to abort during compilation:

thread '' panicked at 'called Option::unwrap() on a None value',
openvaf/mir_llvm/src/context.rs:80:42