MatrixAccel
Matrix multiplication implimented in hardware using verilog hardware description language, and simulated in modelsim
Task 1) includes the schematics and test files for a MAC (Multiply Accumulate Module)
Task 2) control module, and addressing registers for 8x8 matrix multiplication
Task 3) Dual MAC architecture for 8x8 matrix multiplication in 256 Clock Cycles
Task 4) 4 MAC parallel design for 8x8 matrix multiplication in 134 Clock Cycles