diff --git a/core/src/cpus/cortex_m.zig b/core/src/cpus/cortex_m.zig
index 2a8e2e425..d1cee0240 100644
--- a/core/src/cpus/cortex_m.zig
+++ b/core/src/cpus/cortex_m.zig
@@ -2,8 +2,6 @@ const std = @import("std");
 const builtin = @import("builtin");
 const microzig = @import("microzig");
 const mmio = microzig.mmio;
-const app = microzig.app;
-const shared = @import("cortex_m/shared_types.zig");
 const VectorTable = microzig.chip.VectorTable;
 
 const Core = enum {
@@ -1155,7 +1153,7 @@ pub const types = struct {
         /// System Timer (SysTick).
         pub const SysTick = extern struct {
             /// Control and Status Register.
-            CTRL: mmio.Mmio(packed struct(u32) {
+            CTRL: mmio.OldMmio(packed struct(u32) {
                 /// Enables the counter:
                 /// 0 = counter disabled.
                 /// 1 = counter enabled.
@@ -1176,20 +1174,20 @@ pub const types = struct {
                 reserved1: u15 = 0,
             }),
             /// Reload Value Register.
-            LOAD: mmio.Mmio(packed struct(u32) {
+            LOAD: mmio.OldMmio(packed struct(u32) {
                 /// Value to load into the VAL register when the counter is enabled and when it reaches 0.
                 RELOAD: u24,
                 reserved0: u8 = 0,
             }),
             /// Current Value Register.
-            VAL: mmio.Mmio(packed struct(u32) {
+            VAL: mmio.OldMmio(packed struct(u32) {
                 /// Reads return the current value of the SysTick counter.
                 /// A write of any value clears the field to 0, and also clears the CTRL.COUNTFLAG bit to 0.
                 CURRENT: u24,
                 reserved0: u8 = 0,
             }),
             /// Calibration Register.
-            CALIB: mmio.Mmio(packed struct(u32) {
+            CALIB: mmio.OldMmio(packed struct(u32) {
                 /// Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value
                 /// reads as zero, the calibration value is not known.
                 TENMS: u24,
diff --git a/core/src/cpus/cortex_m/m0.zig b/core/src/cpus/cortex_m/m0.zig
index 1e5d8927c..50443c323 100644
--- a/core/src/cpus/cortex_m/m0.zig
+++ b/core/src/cpus/cortex_m/m0.zig
@@ -1,7 +1,5 @@
 const microzig = @import("microzig");
-const builtin = @import("builtin");
 const mmio = microzig.mmio;
-const shared = @import("shared_types.zig");
 
 pub const scb_base_offset = 0x0d00;
 
@@ -9,7 +7,7 @@ pub const SystemControlBlock = extern struct {
     /// CPUID Base Register.
     CPUID: u32,
     /// Interrupt Control and State Register.
-    ICSR: mmio.Mmio(packed struct(u32) {
+    ICSR: mmio.OldMmio(packed struct(u32) {
         /// Contains the active exception number:
         /// 0 = Thread mode
         /// Nonzero = The exception number[a] of the currently active exception.
@@ -79,7 +77,7 @@ pub const SystemControlBlock = extern struct {
     }),
     reserved0: u32 = 0,
     /// Application Interrupt and Reset Control Register.
-    AIRCR: mmio.Mmio(packed struct {
+    AIRCR: mmio.OldMmio(packed struct {
         reserved0: u1 = 0,
         /// Reserved for debug use. This bit reads as 0. When writing to the register you must
         /// write 0 to this bit, otherwise behavior is Unpredictable.
@@ -101,7 +99,7 @@ pub const SystemControlBlock = extern struct {
         VECTKEY: u16,
     }),
     /// System Control Register.
-    SCR: mmio.Mmio(packed struct(u32) {
+    SCR: mmio.OldMmio(packed struct(u32) {
         reserved0: u1 = 0,
         /// Indicates sleep-on-exit when returning from Handler mode to Thread mode:
         /// 0 = do not sleep when returning to Thread mode.
@@ -130,7 +128,7 @@ pub const SystemControlBlock = extern struct {
         reserved2: u27 = 0,
     }),
     /// Configuration Control Register.
-    CCR: mmio.Mmio(packed struct(u32) {
+    CCR: mmio.OldMmio(packed struct(u32) {
         reserved0: u3 = 0,
         /// Always reads as one, indicates that all unaligned accesses generate a HardFault.
         UNALIGN_TRP: u1,
diff --git a/core/src/cpus/cortex_m/m0plus.zig b/core/src/cpus/cortex_m/m0plus.zig
index 7aedb4113..9f284be9d 100644
--- a/core/src/cpus/cortex_m/m0plus.zig
+++ b/core/src/cpus/cortex_m/m0plus.zig
@@ -1,15 +1,13 @@
 const microzig = @import("microzig");
 const mmio = microzig.mmio;
 
-const shared = @import("shared_types.zig");
-
 pub const scb_base_offset = 0x0d00;
 
 pub const SystemControlBlock = extern struct {
     /// CPUID Base Register.
     CPUID: u32,
     /// Interrupt Control and State Register.
-    ICSR: mmio.Mmio(packed struct(u32) {
+    ICSR: mmio.OldMmio(packed struct(u32) {
         /// Contains the active exception number:
         /// 0 = Thread mode
         /// Nonzero = The exception number[a] of the currently active exception.
@@ -80,7 +78,7 @@ pub const SystemControlBlock = extern struct {
     /// Vector Table Offset Register.
     VTOR: u32,
     /// Application Interrupt and Reset Control Register.
-    AIRCR: mmio.Mmio(packed struct {
+    AIRCR: mmio.OldMmio(packed struct {
         reserved0: u1 = 0,
         /// Reserved for debug use. This bit reads as 0. When writing to the register you must
         /// write 0 to this bit, otherwise behavior is Unpredictable.
@@ -102,7 +100,7 @@ pub const SystemControlBlock = extern struct {
         VECTKEY: u16,
     }),
     /// System Control Register.
-    SCR: mmio.Mmio(packed struct(u32) {
+    SCR: mmio.OldMmio(packed struct(u32) {
         reserved0: u1 = 0,
         /// Indicates sleep-on-exit when returning from Handler mode to Thread mode:
         /// 0 = do not sleep when returning to Thread mode.
@@ -131,7 +129,7 @@ pub const SystemControlBlock = extern struct {
         reserved2: u27 = 0,
     }),
     /// Configuration Control Register.
-    CCR: mmio.Mmio(packed struct(u32) {
+    CCR: mmio.OldMmio(packed struct(u32) {
         reserved0: u3 = 0,
         /// Always reads as one, indicates that all unaligned accesses generate a HardFault.
         UNALIGN_TRP: u1,
@@ -195,8 +193,8 @@ pub const NestedVectorInterruptController = extern struct {
 };
 
 pub const MemoryProtectionUnit = extern struct {
-    /// MPU Type Register
-    TYPE: mmio.Mmio(packed struct(u32) {
+    /// MPU Type Register.
+    TYPE: mmio.OldMmio(packed struct(u32) {
         /// Indicates support for unified or separate instructions and data address regions.
         SEPARATE: u1,
         reserved0: u7 = 0,
@@ -206,8 +204,8 @@ pub const MemoryProtectionUnit = extern struct {
         IREGION: u8,
         reserved1: u8 = 0,
     }),
-    /// MPU Control Register
-    CTRL: mmio.Mmio(packed struct(u32) {
+    /// MPU Control Register.
+    CTRL: mmio.OldMmio(packed struct(u32) {
         /// Enables the MPU
         ENABLE: u1,
         /// Enables of operation of MPU during HardFault and MNIHandlers.
@@ -216,14 +214,14 @@ pub const MemoryProtectionUnit = extern struct {
         PRIVDEFENA: u1,
         reserved0: u29 = 0,
     }),
-    /// MPU Region Number Register
-    RNR: mmio.Mmio(packed struct(u32) {
+    /// MPU Region Number Register.
+    RNR: mmio.OldMmio(packed struct(u32) {
         /// Indicates the memory region accessed by MPU RBAR and PMU RLAR.
         REGION: u8,
         reserved0: u24 = 0,
     }),
-    /// MPU Region Base Address Register
-    RBAR: mmio.Mmio(packed struct(u32) {
+    /// MPU Region Base Address Register.
+    RBAR: mmio.OldMmio(packed struct(u32) {
         /// MPU region field.
         REGION: u4,
         /// MPU region number valid bit.
@@ -231,8 +229,8 @@ pub const MemoryProtectionUnit = extern struct {
         /// Region base address field.
         ADDR: u27,
     }),
-    /// MPU Attribute and Size Register
-    RASR: mmio.Mmio(packed struct(u32) {
+    /// MPU Attribute and Size Register.
+    RASR: mmio.OldMmio(packed struct(u32) {
         /// Region enable bit.
         ENABLE: u1,
         /// Specifies the size of the MPU region. The minimum permitted value is 7 (b00111).
diff --git a/core/src/cpus/cortex_m/m3.zig b/core/src/cpus/cortex_m/m3.zig
index 7ec731d22..bdb164abb 100644
--- a/core/src/cpus/cortex_m/m3.zig
+++ b/core/src/cpus/cortex_m/m3.zig
@@ -9,7 +9,7 @@ pub const SystemControlBlock = extern struct {
     /// CPUID Base Register.
     CPUID: u32,
     /// Interrupt Control and State Register.
-    ICSR: mmio.Mmio(packed struct(u32) {
+    ICSR: mmio.OldMmio(packed struct(u32) {
         VECTACTIVE: u9,
         reserved0: u2 = 0,
         RETTOBASE: u1,
@@ -28,7 +28,7 @@ pub const SystemControlBlock = extern struct {
     /// Vector Table Offset Register.
     VTOR: u32,
     /// Application Interrupt and Reset Control Register.
-    AIRCR: mmio.Mmio(packed struct {
+    AIRCR: mmio.OldMmio(packed struct {
         VECTRESET: u1,
         VECTCLRACTIVE: u1,
         SYSRESETREQ: u1,
@@ -39,7 +39,7 @@ pub const SystemControlBlock = extern struct {
         VECTKEY: u16,
     }),
     /// System Control Register.
-    SCR: mmio.Mmio(packed struct {
+    SCR: mmio.OldMmio(packed struct {
         reserved0: u1 = 0,
         SLEEPONEXIT: u1,
         SLEEPDEEP: u1,
@@ -48,7 +48,7 @@ pub const SystemControlBlock = extern struct {
         reserved2: u27 = 0,
     }),
     /// Configuration Control Register.
-    CCR: mmio.Mmio(packed struct(u32) {
+    CCR: mmio.OldMmio(packed struct(u32) {
         NONBASETHRDENA: u1,
         USERSETMPEND: u1,
         reserved0: u1 = 0,
@@ -62,9 +62,9 @@ pub const SystemControlBlock = extern struct {
     /// System Handlers Priority Registers.
     SHPR: [3]u32,
     /// System Handler Control and State Register.
-    SHCSR: mmio.Mmio(shared.scb.SHCSR),
+    SHCSR: mmio.OldMmio(shared.scb.SHCSR),
     /// Configurable Fault Status Register.
-    CFSR: mmio.Mmio(packed struct(u32) {
+    CFSR: mmio.OldMmio(packed struct(u32) {
         /// MemManage Fault Register.
         MMFSR: shared.scb.MMFSR,
         /// BusFault Status Register.
@@ -73,7 +73,7 @@ pub const SystemControlBlock = extern struct {
         UFSR: shared.scb.UFSR,
     }),
     /// HardFault Status Register.
-    HFSR: mmio.Mmio(shared.scb.HFSR),
+    HFSR: mmio.OldMmio(shared.scb.HFSR),
     reserved1: u32 = 0,
     /// MemManage Fault Address Register.
     MMFAR: u32,
@@ -108,7 +108,7 @@ pub const NestedVectorInterruptController = extern struct {
 
 pub const MemoryProtectionUnit = extern struct {
     /// MPU Type Register
-    TYPE: mmio.Mmio(packed struct(u32) {
+    TYPE: mmio.OldMmio(packed struct(u32) {
         /// Indicates support for unified or separate instructions and data address regions.
         SEPARATE: u1,
         reserved0: u7 = 0,
@@ -119,7 +119,7 @@ pub const MemoryProtectionUnit = extern struct {
         reserved1: u8 = 0,
     }),
     /// MPU Control Register
-    CTRL: mmio.Mmio(packed struct(u32) {
+    CTRL: mmio.OldMmio(packed struct(u32) {
         /// Enables the MPU
         ENABLE: u1,
         /// Enables of operation of MPU during HardFault and MNIHandlers.
@@ -129,7 +129,7 @@ pub const MemoryProtectionUnit = extern struct {
         reserved0: u29 = 0,
     }),
     /// MPU Region Number Register
-    RNR: mmio.Mmio(packed struct(u32) {
+    RNR: mmio.OldMmio(packed struct(u32) {
         /// Indicates the memory region accessed by MPU RBAR and PMU RLAR.
         REGION: u8,
         reserved0: u24 = 0,
@@ -151,7 +151,7 @@ pub const MemoryProtectionUnit = extern struct {
     /// MPU Alias 3 Region Attribute and Size Register
     RASR_A3: RASR_Register,
 
-    pub const RBAR_Register = mmio.Mmio(packed struct(u32) {
+    pub const RBAR_Register = mmio.OldMmio(packed struct(u32) {
         /// MPU region field.
         REGION: u4,
         /// MPU region number valid bit.
@@ -160,7 +160,7 @@ pub const MemoryProtectionUnit = extern struct {
         ADDR: u27,
     });
 
-    pub const RASR_Register = mmio.Mmio(packed struct(u32) {
+    pub const RASR_Register = mmio.OldMmio(packed struct(u32) {
         /// Region enable bit.
         ENABLE: u1,
         /// Specifies the size of the MPU protection region.
diff --git a/core/src/cpus/cortex_m/m33.zig b/core/src/cpus/cortex_m/m33.zig
index 3e93d5f96..825a7b6c5 100644
--- a/core/src/cpus/cortex_m/m33.zig
+++ b/core/src/cpus/cortex_m/m33.zig
@@ -18,7 +18,7 @@ pub const SystemControlBlock = extern struct {
     /// CPUID Base Register.
     CPUID: u32,
     /// Interrupt Control and State Register.
-    ICSR: mmio.Mmio(packed struct(u32) {
+    ICSR: mmio.OldMmio(packed struct(u32) {
         /// Contains the active exception number:
         /// 0 = Thread mode
         /// Nonzero = The exception number[a] of the currently active exception.
@@ -36,7 +36,7 @@ pub const SystemControlBlock = extern struct {
         /// Interrupt pending flag, excluding NMI and Faults:
         /// 0 = interrupt not pending
         /// 1 = interrupt pending.
-        ISRPENDING: u1 = 0,
+        ISRPENDING: u1,
         /// Indicates whether a pending exception will be serviced on exit from debug
         /// halt state:
         /// 0 = will not be serviced
@@ -109,7 +109,7 @@ pub const SystemControlBlock = extern struct {
     /// Vector Table Offset Register.
     VTOR: u32,
     /// Application Interrupt and Reset Control Register.
-    AIRCR: mmio.Mmio(packed struct {
+    AIRCR: mmio.OldMmio(packed struct {
         reserved0: u1 = 0,
         /// Reserved for debug use. This bit reads as 0. When writing to the register you must
         /// write 0 to this bit, otherwise behavior is Unpredictable.
@@ -160,7 +160,7 @@ pub const SystemControlBlock = extern struct {
         VECTKEY: u16,
     }),
     /// System Control Register.
-    SCR: mmio.Mmio(packed struct(u32) {
+    SCR: mmio.OldMmio(packed struct(u32) {
         reserved0: u1 = 0,
         /// Indicates sleep-on-exit when returning from Handler mode to Thread mode:
         /// 0 = do not sleep when returning to Thread mode.
@@ -192,7 +192,7 @@ pub const SystemControlBlock = extern struct {
         reserved1: u27 = 0,
     }),
     /// Configuration and Control Register.
-    CCR: mmio.Mmio(packed struct(u32) {
+    CCR: mmio.OldMmio(packed struct(u32) {
         reserved0: u1 = 0,
         /// User set pending determines if unpriviledged access to the STIR generates a fault.
         USERSETMPEND: u1,
@@ -219,9 +219,9 @@ pub const SystemControlBlock = extern struct {
     /// System Handler Priority Registers.
     SHPR: [12]u8,
     /// System Handler Control and State Register.
-    SHCSR: mmio.Mmio(shared.scb.SHCSR),
+    SHCSR: mmio.OldMmio(shared.scb.SHCSR),
     /// Configurable Fault Status Register.
-    CFSR: mmio.Mmio(packed struct(u32) {
+    CFSR: mmio.OldMmio(packed struct(u32) {
         /// MemManage Fault Register.
         MMFSR: shared.scb.MMFSR,
         /// BusFault Status Register.
@@ -230,7 +230,7 @@ pub const SystemControlBlock = extern struct {
         UFSR: shared.scb.UFSR,
     }),
     /// HardFault Status Register.
-    HFSR: mmio.Mmio(shared.scb.HFSR),
+    HFSR: mmio.OldMmio(shared.scb.HFSR),
     reserved0: u32 = 0,
     /// MemManage Fault Address Register.
     MMFAR: u32,
@@ -240,7 +240,7 @@ pub const SystemControlBlock = extern struct {
     _AFSR: u32,
     reserved1: [18]u32,
     /// Coprocessor Access Control Register.
-    CPACR: mmio.Mmio(packed struct(u32) {
+    CPACR: mmio.OldMmio(packed struct(u32) {
         CP0: Privilege,
         CP1: Privilege,
         CP2: Privilege,
@@ -269,7 +269,7 @@ pub const SystemControlBlock = extern struct {
 };
 
 pub const FloatingPointUnit = extern struct {
-    FPCCR: mmio.Mmio(packed struct(u32) {
+    FPCCR: mmio.OldMmio(packed struct(u32) {
         LSPACT: u1,
         USER: u1,
         S: u1,
@@ -382,7 +382,7 @@ pub const SecurityAttributionUnit = extern struct {
 
 pub const MemoryProtectionUnit = extern struct {
     /// MPU Type Register.
-    TYPE: mmio.Mmio(packed struct(u32) {
+    TYPE: mmio.OldMmio(packed struct(u32) {
         /// Indicates support for unified or separate instructions and data address regions.
         SEPARATE: u1,
         reserved0: u7 = 0,
@@ -391,7 +391,7 @@ pub const MemoryProtectionUnit = extern struct {
         reserved1: u16 = 0,
     }),
     /// MPU Control Register.
-    CTRL: mmio.Mmio(packed struct(u32) {
+    CTRL: mmio.OldMmio(packed struct(u32) {
         /// Enables the MPU
         ENABLE: u1,
         /// Enables of operation of MPU during HardFault and MNIHandlers.
@@ -401,7 +401,7 @@ pub const MemoryProtectionUnit = extern struct {
         reserved0: u29 = 0,
     }),
     /// MPU Region Number Register.
-    RNR: mmio.Mmio(packed struct(u32) {
+    RNR: mmio.OldMmio(packed struct(u32) {
         /// Indicates the memory region accessed by MPU RBAR and PMU RLAR.
         REGION: u8,
         reserved0: u24 = 0,
@@ -429,7 +429,7 @@ pub const MemoryProtectionUnit = extern struct {
     MPU_MAIR1: u32,
 
     /// MPU Region Address Register format.
-    pub const RBAR_Register = mmio.Mmio(packed struct(u32) {
+    pub const RBAR_Register = mmio.OldMmio(packed struct(u32) {
         /// Execute Never defines if code can be executed from this region.
         XN: u1,
         /// Access permissions.
@@ -442,7 +442,7 @@ pub const MemoryProtectionUnit = extern struct {
     });
 
     /// MPU Region Limit Address Register format.
-    pub const RLAR_Register = mmio.Mmio(packed struct(u32) {
+    pub const RLAR_Register = mmio.OldMmio(packed struct(u32) {
         /// Enable the region.
         EN: u1,
         /// Attribue Index associates a set of attributes in the MPU MAIR0 and MPU MAIR1 fields.
diff --git a/core/src/cpus/cortex_m/m4.zig b/core/src/cpus/cortex_m/m4.zig
index 0fb631508..2e2cbc9cc 100644
--- a/core/src/cpus/cortex_m/m4.zig
+++ b/core/src/cpus/cortex_m/m4.zig
@@ -9,7 +9,7 @@ pub const SystemControlBlock = extern struct {
     /// CPUID Base Register.
     CPUID: u32,
     /// Interrupt Control and State Register.
-    ICSR: mmio.Mmio(packed struct(u32) {
+    ICSR: mmio.OldMmio(packed struct(u32) {
         VECTACTIVE: u9,
         reserved0: u2 = 0,
         RETTOBASE: u1,
@@ -28,7 +28,7 @@ pub const SystemControlBlock = extern struct {
     /// Vector Table Offset Register.
     VTOR: u32,
     /// Application Interrupt and Reset Control Register.
-    AIRCR: mmio.Mmio(packed struct {
+    AIRCR: mmio.OldMmio(packed struct {
         VECTRESET: u1,
         VECTCLRACTIVE: u1,
         SYSRESETREQ: u1,
@@ -39,7 +39,7 @@ pub const SystemControlBlock = extern struct {
         VECTKEY: u16,
     }),
     /// System Control Register.
-    SCR: mmio.Mmio(packed struct {
+    SCR: mmio.OldMmio(packed struct {
         reserved0: u1 = 0,
         SLEEPONEXIT: u1,
         SLEEPDEEP: u1,
@@ -48,7 +48,7 @@ pub const SystemControlBlock = extern struct {
         reserved2: u27 = 0,
     }),
     /// Configuration Control Register.
-    CCR: mmio.Mmio(packed struct(u32) {
+    CCR: mmio.OldMmio(packed struct(u32) {
         NONBASETHRDENA: u1,
         USERSETMPEND: u1,
         reserved0: u1 = 0,
@@ -62,9 +62,9 @@ pub const SystemControlBlock = extern struct {
     /// System Handlers Priority Registers.
     SHP: [12]u8,
     /// System Handler Contol and State Register.
-    SHCSR: mmio.Mmio(shared.scb.SHCSR),
+    SHCSR: mmio.OldMmio(shared.scb.SHCSR),
     /// Configurable Fault Status Register.
-    CFSR: mmio.Mmio(packed struct(u32) {
+    CFSR: mmio.OldMmio(packed struct(u32) {
         /// MemManage Fault Register.
         MMFSR: shared.scb.MMFSR,
         /// BusFault Status Register.
@@ -73,7 +73,7 @@ pub const SystemControlBlock = extern struct {
         UFSR: shared.scb.UFSR,
     }),
     /// HardFault Status Register.
-    HFSR: mmio.Mmio(shared.scb.HFSR),
+    HFSR: mmio.OldMmio(shared.scb.HFSR),
     /// Debug Fault Status Register.
     DFSR: u32,
     /// MemManage Fault Address Register.
@@ -83,7 +83,7 @@ pub const SystemControlBlock = extern struct {
     /// Auxilary Feature Register.
     AFSR: u32,
     reserved0: [18]u32,
-    CPACR: mmio.Mmio(packed struct(u32) {
+    CPACR: mmio.OldMmio(packed struct(u32) {
         reserved0: u20,
         CP10: Privilege,
         CP11: Privilege,
@@ -126,7 +126,7 @@ pub const NestedVectorInterruptController = extern struct {
 
 pub const MemoryProtectionUnit = extern struct {
     /// MPU Type Register.
-    TYPE: mmio.Mmio(packed struct(u32) {
+    TYPE: mmio.OldMmio(packed struct(u32) {
         /// Indicates support for unified or separate instructions and data address regions.
         SEPARATE: u1,
         reserved0: u7 = 0,
@@ -137,7 +137,7 @@ pub const MemoryProtectionUnit = extern struct {
         reserved1: u8 = 0,
     }),
     /// MPU Control Register.
-    CTRL: mmio.Mmio(packed struct(u32) {
+    CTRL: mmio.OldMmio(packed struct(u32) {
         /// Enables the MPU.
         ENABLE: u1,
         /// Enables of operation of MPU during HardFault and MNIHandlers.
@@ -147,7 +147,7 @@ pub const MemoryProtectionUnit = extern struct {
         reserved0: u29 = 0,
     }),
     /// MPU Region Number Register.
-    RNR: mmio.Mmio(packed struct(u32) {
+    RNR: mmio.OldMmio(packed struct(u32) {
         /// Indicates the memory region accessed by MPU RBAR and PMU RLAR.
         REGION: u8,
         reserved0: u24 = 0,
@@ -169,7 +169,7 @@ pub const MemoryProtectionUnit = extern struct {
     /// MPU Alias 3 Region Attribute and Size Register.
     RASR_A3: RASR_Register,
 
-    pub const RBAR_Register = mmio.Mmio(packed struct(u32) {
+    pub const RBAR_Register = mmio.OldMmio(packed struct(u32) {
         /// MPU region field.
         REGION: u4,
         /// MPU region number valid bit.
@@ -178,7 +178,7 @@ pub const MemoryProtectionUnit = extern struct {
         ADDR: u27,
     });
 
-    pub const RASR_Register = mmio.Mmio(packed struct(u32) {
+    pub const RASR_Register = mmio.OldMmio(packed struct(u32) {
         /// Region enable bit.
         ENABLE: u1,
         /// Specifies the size of the MPU protection region.
@@ -204,7 +204,7 @@ pub const MemoryProtectionUnit = extern struct {
 };
 
 pub const FloatingPointUnit = extern struct {
-    FPCCR: mmio.Mmio(packed struct(u32) {
+    FPCCR: mmio.OldMmio(packed struct(u32) {
         LSPACT: u1,
         USER: u1,
         reserved0: u1 = 0,
diff --git a/core/src/cpus/cortex_m/m55.zig b/core/src/cpus/cortex_m/m55.zig
index 467adfc9f..ed8518705 100644
--- a/core/src/cpus/cortex_m/m55.zig
+++ b/core/src/cpus/cortex_m/m55.zig
@@ -13,7 +13,7 @@ pub const SystemControlBlock = extern struct {
     /// CPUID Base Register.
     CPUID: u32,
     /// Interrupt Control and State Register.
-    ICSR: mmio.Mmio(packed struct(u32) {
+    ICSR: mmio.OldMmio(packed struct(u32) {
         /// Contains the active exception number:
         /// 0 = Thread mode
         /// Nonzero = The exception number[a] of the currently active exception.
@@ -104,7 +104,7 @@ pub const SystemControlBlock = extern struct {
     /// Vector Table Offset Register.
     VTOR: u32,
     /// Application Interrupt and Reset Control Register.
-    AIRCR: mmio.Mmio(packed struct {
+    AIRCR: mmio.OldMmio(packed struct {
         reserved0: u1 = 0,
         /// Reserved for debug use. This bit reads as 0. When writing to the register you must
         /// write 0 to this bit, otherwise behavior is Unpredictable.
@@ -157,7 +157,7 @@ pub const SystemControlBlock = extern struct {
     /// System Control Register.
     SCR: u32,
     /// Configuration and Control Register.
-    CCR: mmio.Mmio(packed struct(u32) {
+    CCR: mmio.OldMmio(packed struct(u32) {
         reserved0: u1 = 0,
         /// User set pending determines if unpriviledged access to the STIR generates a fault.
         USERSETMPEND: u1,
@@ -184,9 +184,9 @@ pub const SystemControlBlock = extern struct {
     /// System Handler Priority Registers.
     SHPR: [12]u8,
     /// System Handler Control and State Register.
-    SHCSR: mmio.Mmio(shared.scb.SHCSR),
+    SHCSR: mmio.OldMmio(shared.scb.SHCSR),
     /// Configurable Fault Status Register.
-    CFSR: mmio.Mmio(packed struct(u32) {
+    CFSR: mmio.OldMmio(packed struct(u32) {
         /// MemManage Fault Register.
         MMFSR: shared.scb.MMFSR,
         /// BusFault Status Register.
@@ -195,7 +195,7 @@ pub const SystemControlBlock = extern struct {
         UFSR: shared.scb.UFSR,
     }),
     /// HardFault Status Register.
-    HFSR: mmio.Mmio(shared.scb.HFSR),
+    HFSR: mmio.OldMmio(shared.scb.HFSR),
     /// Debug Fault Status Register.
     DFSR: u32,
     /// MemManage Fault Address Register.
@@ -273,7 +273,7 @@ pub const SecurityAttributionUnit = extern struct {
 
 pub const MemoryProtectionUnit = extern struct {
     /// MPU Type Register.
-    TYPE: mmio.Mmio(packed struct(u32) {
+    TYPE: mmio.OldMmio(packed struct(u32) {
         /// Indicates support for unified or separate instructions and data address regions.
         SEPARATE: u1,
         reserved0: u7 = 0,
@@ -282,7 +282,7 @@ pub const MemoryProtectionUnit = extern struct {
         reserved1: u16 = 0,
     }),
     /// MPU Control Register.
-    CTRL: mmio.Mmio(packed struct(u32) {
+    CTRL: mmio.OldMmio(packed struct(u32) {
         /// Enables the MPU
         ENABLE: u1,
         /// Enables of operation of MPU during HardFault and MNIHandlers.
@@ -292,7 +292,7 @@ pub const MemoryProtectionUnit = extern struct {
         reserved0: u29 = 0,
     }),
     /// MPU Region Number Register.
-    RNR: mmio.Mmio(packed struct(u32) {
+    RNR: mmio.OldMmio(packed struct(u32) {
         /// Indicates the memory region accessed by MPU RBAR and PMU RLAR.
         REGION: u8,
         reserved0: u24 = 0,
@@ -320,7 +320,7 @@ pub const MemoryProtectionUnit = extern struct {
     MPU_MAIR1: u32,
 
     /// MPU Region Address Register format.
-    pub const RBAR_Register = mmio.Mmio(packed struct(u32) {
+    pub const RBAR_Register = mmio.OldMmio(packed struct(u32) {
         /// Execute Never defines if code can be executed from this region.
         XN: u1,
         /// Access permissions.
@@ -333,7 +333,7 @@ pub const MemoryProtectionUnit = extern struct {
     });
 
     /// MPU Region Limit Address Register format.
-    pub const RLAR_Register = mmio.Mmio(packed struct(u32) {
+    pub const RLAR_Register = mmio.OldMmio(packed struct(u32) {
         /// Enable the region.
         EN: u1,
         /// Attribue Index associates a set of attributes in the MPU MAIR0 and MPU MAIR1 fields.
diff --git a/core/src/cpus/cortex_m/m7.zig b/core/src/cpus/cortex_m/m7.zig
index 9127054ed..18b41f51b 100644
--- a/core/src/cpus/cortex_m/m7.zig
+++ b/core/src/cpus/cortex_m/m7.zig
@@ -6,10 +6,10 @@ const shared = @import("shared_types.zig");
 pub const scb_base_offset = 0x0d00;
 
 pub const SystemControlBlock = extern struct {
-    /// CPUID Base Register
+    /// CPUID Base Register.
     CPUID: u32,
-    /// Interrupt Control and State Register
-    ICSR: mmio.Mmio(packed struct(u32) {
+    /// Interrupt Control and State Register.
+    ICSR: mmio.OldMmio(packed struct(u32) {
         VECTACTIVE: u9,
         reserved0: u2 = 0,
         RETTOBASE: u1,
@@ -25,10 +25,10 @@ pub const SystemControlBlock = extern struct {
         reserved3: u2 = 0,
         NMIPENDSET: u1,
     }),
-    /// Vector Table Offset Register
+    /// Vector Table Offset Register.
     VTOR: u32,
-    /// Application Interrupt and Reset Control Register
-    AIRCR: mmio.Mmio(packed struct(u32) {
+    /// Application Interrupt and Reset Control Register.
+    AIRCR: mmio.OldMmio(packed struct(u32) {
         /// Reserved for Debug use. Must be written as 0.
         VECTRESET: u1, // WO
         /// Reserved for Debug use. Must be written as 0.
@@ -46,8 +46,8 @@ pub const SystemControlBlock = extern struct {
     }),
     /// System Control Register
     SCR: u32,
-    /// Configuration Control Register
-    CCR: mmio.Mmio(packed struct(u32) {
+    /// Configuration Control Register.
+    CCR: mmio.OldMmio(packed struct(u32) {
         NONBASETHRDENA: u1,
         USERSETMPEND: u1,
         reserved0: u1 = 0,
@@ -67,7 +67,7 @@ pub const SystemControlBlock = extern struct {
     }),
 
     /// System Handler Priority Register 1 (SHPR1)
-    SHPR1: mmio.Mmio(packed struct(u32) {
+    SHPR1: mmio.OldMmio(packed struct(u32) {
         /// Priority of system handler 4, MemManage
         PRI_4: u8,
         /// Priority of system handler 5, BusFault
@@ -79,7 +79,7 @@ pub const SystemControlBlock = extern struct {
     }),
 
     /// System Handler Priority Register 2 (SHPR2)
-    SHPR2: mmio.Mmio(packed struct(u32) {
+    SHPR2: mmio.OldMmio(packed struct(u32) {
         /// Reserved bits [23:0]
         reserved0: u24 = 0,
         /// Priority of system handler 11, SVCall
@@ -87,7 +87,7 @@ pub const SystemControlBlock = extern struct {
     }),
 
     /// System Handler Priority Register 3 (SHPR3)
-    SHPR3: mmio.Mmio(packed struct(u32) {
+    SHPR3: mmio.OldMmio(packed struct(u32) {
         /// Reserved bits [15:0]
         reserved0: u16 = 0,
         /// Priority of system handler 14, PendSV
@@ -97,9 +97,9 @@ pub const SystemControlBlock = extern struct {
     }),
 
     /// System Handler Contol and State Register
-    SHCSR: mmio.Mmio(shared.scb.SHCSR),
+    SHCSR: mmio.OldMmio(shared.scb.SHCSR),
     /// Configurable Fault Status Register
-    CFSR: mmio.Mmio(packed struct(u32) {
+    CFSR: mmio.OldMmio(packed struct(u32) {
         /// MemManage Fault Register.
         MMFSR: shared.scb.MMFSR,
         /// BusFault Status Register.
@@ -114,7 +114,7 @@ pub const SystemControlBlock = extern struct {
     /// UsageFault Status Register
     UFSR: u32,
     /// HardFault Status Register
-    HFSR: mmio.Mmio(shared.scb.HFSR),
+    HFSR: mmio.OldMmio(shared.scb.HFSR),
     /// MemManage Fault Address Register
     MMAR: u32,
     /// BusFault Address Register
@@ -170,7 +170,7 @@ pub const NestedVectorInterruptController = extern struct {
 
 pub const MemoryProtectionUnit = extern struct {
     /// MPU Type Register
-    TYPE: mmio.Mmio(packed struct(u32) {
+    TYPE: mmio.OldMmio(packed struct(u32) {
         SEPARATE: u1,
         reserved0: u7 = 0,
         DREGION: u8,
@@ -178,14 +178,14 @@ pub const MemoryProtectionUnit = extern struct {
         reserved1: u8 = 0,
     }),
     /// MPU Control Register
-    CTRL: mmio.Mmio(packed struct(u32) {
+    CTRL: mmio.OldMmio(packed struct(u32) {
         ENABLE: u1,
         HFNMIENA: u1,
         PRIVDEFENA: u1,
         padding: u29 = 0,
     }),
     /// MPU RNRber Register
-    RNR: mmio.Mmio(packed struct(u32) {
+    RNR: mmio.OldMmio(packed struct(u32) {
         REGION: u8,
         padding: u24 = 0,
     }),
@@ -206,13 +206,13 @@ pub const MemoryProtectionUnit = extern struct {
     /// MPU Alias 3 Region Attribute and Size Register
     RASR_A3: RASR_Register,
 
-    pub const RBAR_Register = mmio.Mmio(packed struct(u32) {
+    pub const RBAR_Register = mmio.OldMmio(packed struct(u32) {
         REGION: u4,
         VALID: u1,
         ADDR: u27,
     });
 
-    pub const RASR_Register = mmio.Mmio(packed struct(u32) {
+    pub const RASR_Register = mmio.OldMmio(packed struct(u32) {
         /// Region enable bit
         ENABLE: u1,
         /// Region Size
@@ -239,7 +239,7 @@ pub const MemoryProtectionUnit = extern struct {
 
 pub const DebugRegisters = extern struct {
     /// Debyg Halting Control and Status Register
-    DHCSR: mmio.Mmio(packed struct {
+    DHCSR: mmio.OldMmio(packed struct {
         reserved0: u6 = 0,
         S_RESET_ST: u1,
         S_RETIRE_ST: u1,
@@ -258,18 +258,18 @@ pub const DebugRegisters = extern struct {
     }),
     /// Debug Core Register Selector Register
     /// TODO: Reserved have values ? see armv7-m reference manual
-    DCRSR: mmio.Mmio(packed struct {
+    DCRSR: mmio.OldMmio(packed struct {
         reserved0: u15 = 0,
         REGWnR: u1,
         reserved1: u9 = 0,
         REGSEL: u7,
     }),
     /// Debug Core Register Data Register
-    DCRDR: mmio.Mmio(packed struct {
+    DCRDR: mmio.OldMmio(packed struct {
         DBGTMP: u32,
     }),
     /// Debug exception and Monitor Control Register
-    DEMCR: mmio.Mmio(packed struct {
+    DEMCR: mmio.OldMmio(packed struct {
         reserved0: u7 = 0,
         TRCENA: u1,
         reserved1: u4 = 0,
@@ -292,7 +292,7 @@ pub const DebugRegisters = extern struct {
 
 pub const ITM = extern struct {
     /// Stimulus Port Registers (0-255)
-    STIM: [256]mmio.Mmio(packed union {
+    STIM: [256]mmio.OldMmio(packed union {
         WRITE_U8: u8,
         WRITE_U16: u16,
         WRITE_U32: u32,
@@ -305,21 +305,21 @@ pub const ITM = extern struct {
     reserved0: [640]u32, // Padding to 0xE00
 
     /// Trace Enable Registers (0-7)
-    TER: [8]mmio.Mmio(packed struct(u32) {
+    TER: [8]mmio.OldMmio(packed struct(u32) {
         STIMENA: u32, // Enable bits for stimulus ports
     }),
 
     reserved1: [10]u32, // Padding to 0xE40
 
     /// Trace Privilege Register
-    TPR: mmio.Mmio(packed struct(u32) {
+    TPR: mmio.OldMmio(packed struct(u32) {
         PRIVMASK: u32, // Privilege mask for stimulus ports
     }),
 
     reserved2: [15]u32, // Padding to 0xE80
 
     /// Trace Control Register
-    TCR: mmio.Mmio(packed struct(u32) {
+    TCR: mmio.OldMmio(packed struct(u32) {
         ITMENA: u1, // ITM enable
         TSENA: u1, // Local timestamp enable
         SYNCENA: u1, // Sync packet enable
@@ -337,28 +337,28 @@ pub const ITM = extern struct {
 
 pub const TPIU = extern struct {
     /// Supported Parallel Port Sizes Register
-    SSPSR: mmio.Mmio(packed struct(u32) {
+    SSPSR: mmio.OldMmio(packed struct(u32) {
         SWIDTH: u32,
     }),
     /// Current Parallel Port Size Register
-    CSPSR: mmio.Mmio(packed struct(u32) {
+    CSPSR: mmio.OldMmio(packed struct(u32) {
         CWIDTH: u32,
     }),
     reserved0: [2]u32,
     /// Asynchronous Clock Prescaler Register
-    ACPR: mmio.Mmio(packed struct(u32) {
+    ACPR: mmio.OldMmio(packed struct(u32) {
         SWOSCALER: u16,
         padding: u16 = 0,
     }),
     reserved1: [55]u32,
     /// Selected Pin Protocol Register
-    SPPR: mmio.Mmio(packed struct(u32) {
+    SPPR: mmio.OldMmio(packed struct(u32) {
         TXMODE: u2,
         padding: u30 = 0,
     }),
     reserved2: [524]u32,
     /// TPIU Type Register
-    TYPE: mmio.Mmio(packed struct(u32) {
+    TYPE: mmio.OldMmio(packed struct(u32) {
         reserved0: u6 = 0,
         FIFOSZ: u3,
         PTINVALID: u1,
@@ -371,7 +371,7 @@ pub const TPIU = extern struct {
 };
 
 pub const FloatingPointUnit = extern struct {
-    FPCCR: mmio.Mmio(packed struct(u32) {
+    FPCCR: mmio.OldMmio(packed struct(u32) {
         LSPACT: u1,
         USER: u1,
         S: u1,
diff --git a/core/src/mmio.zig b/core/src/mmio.zig
index 98c08579a..d14007ab8 100644
--- a/core/src/mmio.zig
+++ b/core/src/mmio.zig
@@ -1,97 +1,263 @@
 const std = @import("std");
-const assert = std.debug.assert;
 
-pub fn Mmio(comptime PackedT: type) type {
+pub fn OldMmio(comptime PackedT: type) type {
+    const startsWith = std.mem.startsWith;
+
+    var access: MmioAccess(PackedT) = undefined;
+    for (@typeInfo(PackedT).@"struct".fields) |fld| {
+        const read_only = startsWith(u8, fld.name, "reserved") or
+            startsWith(u8, fld.name, "_reserved") or
+            startsWith(u8, fld.name, "padding");
+        @field(access, fld.name) = if (read_only) .read_only else .read_write;
+    }
+    return Mmio(PackedT, access);
+}
+
+/// Access type of a single field.
+pub const Access = struct {
+    /// Effect of reading the field
+    pub const Read = enum {
+        /// Reading returns the currently stored field value and does not affect it.
+        normal,
+        /// Reading is not an error, but the returned value is meaningless.
+        garbage,
+        /// Reading changes the field value in an implementation-defined way.
+        special,
+        /// This register should never be read from.
+        illegal,
+        // There exist more!
+    };
+
+    pub const Write = enum {
+        /// Writing sets the field value to what was written.
+        normal,
+        /// Writing has no effect.
+        ignored,
+        /// Write 1 to set, 0 to leave unaffected.
+        set_mask,
+        /// Write 1 to clear, 0 to leave unaffected.
+        clear_mask,
+        /// Write 1 to toggle, 0 to leave unaffected.
+        toggle_mask,
+        /// Writing changes the this field in an implementation-defined way.
+        special,
+        /// This register should never be written to.
+        illegal,
+        // There exist more!
+    };
+
+    read: Read,
+    write: Write,
+
+    // Mapping of svd types
+    pub const read_only: @This() = .{ .read = .normal, .write = .ignored };
+    pub const read_write: @This() = .{ .read = .normal, .write = .normal };
+    pub const read_writeonce: @This() = .read_write;
+    pub const write_only: @This() = .{ .read = .garbage, .write = .normal };
+    pub const write_once: @This() = .write_only;
+    pub const read_clear: @This() = .{ .read = .normal, .write = .clear_mask };
+    pub const reserved: @This() = .{ .read = .garbage, .write = .ignored };
+    /// SVD has one of known ambiguous register names, needs a patch.
+    pub const ambiguous: @This() = .{ .read = .illegal, .write = .illegal };
+};
+
+fn check_type_has_all_fields(T: type, fields: anytype) void {
+    inline for (@typeInfo(@TypeOf(fields)).@"struct".fields) |field| {
+        if (!@hasField(T, field.name))
+            @compileError("Field " ++ field.name ++ " not present in " ++ @typeName(T));
+    }
+}
+
+pub fn MmioAccess(comptime PackedT: type) type {
+    @setEvalBranchQuota(20_000);
+    switch (@typeInfo(PackedT)) {
+        .@"struct" => |info| {
+            var field_names: [info.fields.len][:0]const u8 = undefined;
+            for (&field_names, info.fields) |*dst, src|
+                dst.* = src.name;
+            return @import("../src/core/usb.zig").Struct(
+                .auto,
+                null,
+                &field_names,
+                &@splat(Access),
+                &@splat(.{}),
+            );
+        },
+        .int => return Access,
+        else => {},
+    }
+    @compileError("Type " ++ @typeName(PackedT) ++ " cannot be used in Mmio");
+}
+
+pub fn Mmio(comptime PackedT: type, access_type: MmioAccess(PackedT)) type {
     @setEvalBranchQuota(2_000);
 
-    const size = @bitSizeOf(PackedT);
-    if ((size % 8) != 0)
-        @compileError("size must be divisible by 8!");
+    const IntT, const reg_fields = switch (@typeInfo(PackedT)) {
+        .@"struct" => |info| .{ switch (info.layout) {
+            .@"packed" => info.backing_integer.?,
+            else => @compileError("Struct must be packed"),
+        }, info.fields },
+        .int => .{ PackedT, null },
+        else => @compileError("Unsupported type: " ++ @typeName(PackedT)),
+    };
 
-    if (!std.math.isPowerOfTwo(size / 8))
-        @compileError("size must encode a power of two number of bytes!");
+    if (@bitSizeOf(PackedT) != 8 * @sizeOf(PackedT))
+        @compileError("Size in bits must be divisible by 8");
 
-    const IntT = std.meta.Int(.unsigned, size);
+    if (!std.math.isPowerOfTwo(@sizeOf(PackedT)))
+        @compileError("Size in bytes must be a power of two");
 
-    if (@sizeOf(PackedT) != (size / 8))
-        @compileError(std.fmt.comptimePrint("IntT and PackedT must have the same size!, they are {} and {} bytes respectively", .{ size / 8, @sizeOf(PackedT) }));
+    if (@alignOf(PackedT) != @sizeOf(PackedT))
+        @compileError("PackedT must be naturally aligned");
 
-    return extern struct {
-        const Self = @This();
+    if (@sizeOf(IntT) != @sizeOf(PackedT)) @compileError(std.fmt.comptimePrint(
+        "IntT and PackedT must have the same size, they are {} and {} bytes respectively",
+        .{ @sizeOf(IntT), @sizeOf(PackedT) },
+    ));
 
+    if (@bitSizeOf(IntT) != @bitSizeOf(PackedT)) @compileError(std.fmt.comptimePrint(
+        "IntT and PackedT must have the same bitsize, they are {} and {} bits respectively",
+        .{ @bitSizeOf(IntT), @bitSizeOf(PackedT) },
+    ));
+
+    return extern struct {
         raw: IntT,
 
         pub const underlying_type = PackedT;
+        const all_zeros: PackedT = @bitCast(@as(IntT, 0));
 
-        pub inline fn read(addr: *volatile Self) PackedT {
-            return @bitCast(addr.raw);
-        }
-
-        pub inline fn write(addr: *volatile Self, val: PackedT) void {
-            comptime {
-                assert(@bitSizeOf(PackedT) == @bitSizeOf(IntT));
-            }
-            addr.write_raw(@bitCast(val));
+        pub inline fn read(self: *volatile @This()) PackedT {
+            comptime for (reg_fields) |field|
+                switch (@field(access_type, field.name).read) {
+                    .normal, .garbage, .special => {},
+                    .illegal => reg_type_op_error(field.name, "reading from any fields of the register"),
+                };
+            return @bitCast(self.raw);
         }
 
-        pub inline fn write_raw(addr: *volatile Self, val: IntT) void {
-            addr.raw = val;
+        pub inline fn write(self: *volatile @This(), w: PackedT) void {
+            comptime for (reg_fields) |field|
+                switch (@field(access_type, field.name).write) {
+                    .normal, .ignored, .set_mask, .clear_mask, .toggle_mask, .special => {},
+                    .illegal => reg_type_op_error(field.name, "writing to any fields of the register"),
+                };
+            self.raw = @bitCast(w);
         }
 
         /// Set field `field_name` of this register to `value`.
         /// A one-field version of modify(), more helpful if `field_name` is comptime calculated.
-        pub inline fn modify_one(addr: *volatile Self, comptime field_name: []const u8, value: @FieldType(underlying_type, field_name)) void {
-            var val = read(addr);
-            @field(val, field_name) = value;
-            write(addr, val);
+        pub inline fn modify_one(
+            self: *volatile @This(),
+            comptime field_name: [:0]const u8,
+            value: @FieldType(underlying_type, field_name),
+        ) void {
+            // Replace with @Struct when migrating to zig 0.16
+            var fields: @import("core/usb.zig").Struct(
+                .auto,
+                null,
+                &.{field_name},
+                &.{@TypeOf(value)},
+                &.{.{}},
+            ) = undefined;
+            @field(fields, field_name) = value;
+            self.modify(fields);
         }
 
         /// For each `.Field = value` entry of `fields`:
         /// Set field `Field` of this register to `value`.
-        pub inline fn modify(addr: *volatile Self, fields: anytype) void {
-            var val = read(addr);
-            inline for (@typeInfo(@TypeOf(fields)).@"struct".fields) |field| {
-                @field(val, field.name) = @field(fields, field.name);
+        /// This is implemented using read-modify-write.
+        pub inline fn modify(self: *volatile @This(), fields: anytype) void {
+            @setEvalBranchQuota(10_000);
+            check_type_has_all_fields(PackedT, fields);
+            const Fields = @TypeOf(fields);
+
+            const r = self.read();
+            var w: PackedT = undefined;
+            inline for (reg_fields) |field| {
+                const access = @field(access_type, field.name);
+                @field(w, field.name) = if (@hasField(Fields, field.name))
+                    // Overwrite this field
+                    if (access.write == .normal and (access.read == .normal or access.read == .garbage))
+                        @field(fields, field.name)
+                    else
+                        reg_type_op_error(field.name, "modifying this field by read-modify-write")
+                else switch (access.write) {
+                    // Leave field unchanged
+                    .normal => if (access.read == .normal)
+                        @field(r, field.name)
+                    else
+                        // This should actually be:
+                        // reg_type_op_error(field.name, "modifying any field in this register by read-modify-write")
+                        @field(all_zeros, field.name),
+                    // Preserve old functionality
+                    .ignored => @field(r, field.name),
+                    // Write zeros so that nothing happens
+                    .set_mask, .clear_mask, .toggle_mask => @field(all_zeros, field.name),
+                    else => reg_type_op_error(field.name, "modifying any field in this register by read-modify-write"),
+                };
             }
-            write(addr, val);
+            self.write(w);
         }
 
-        /// In field `field_name` of struct `val`, toggle (only) all bits that are set in `value`.
-        inline fn toggle_field(val: anytype, comptime field_name: []const u8, value: anytype) void {
-            const FieldType = @TypeOf(@field(val, field_name));
-            switch (@typeInfo(FieldType)) {
-                .int => {
-                    @field(val, field_name) = @field(val, field_name) ^ value;
-                },
-                .@"enum" => |enum_info| {
-                    // same as for the .Int case, but casting to and from the u... tag type U of the enum FieldType
-                    const U = enum_info.tag_type;
-                    @field(val, field_name) =
-                        @as(FieldType, @enumFromInt(@as(U, @intFromEnum(@field(val, field_name))) ^
-                        @as(U, @intFromEnum(@as(FieldType, value)))));
-                },
-                else => |T| {
-                    @compileError("unsupported register field type '" ++ @typeName(T) ++ "'");
-                },
+        pub inline fn set_mask(self: *volatile @This(), fields: anytype) void {
+            @setEvalBranchQuota(10_000);
+            check_type_has_all_fields(PackedT, fields);
+            const Fields = @TypeOf(fields);
+
+            var w: PackedT = undefined;
+            inline for (reg_fields) |field| {
+                const access = @field(access_type, field.name);
+                @field(w, field.name) = if (@hasField(Fields, field.name))
+                    // Set bits in this field
+                    if (access.write == .set_mask)
+                        @field(fields, field.name)
+                    else
+                        reg_type_op_error(field.name, "setting bits of this field by masking")
+                else switch (access.write) {
+                    // Write zeros so that nothing happens
+                    .ignored, .set_mask, .clear_mask, .toggle_mask => @field(all_zeros, field.name),
+                    else => reg_type_op_error(field.name, "setting bits of any field in this register by masking"),
+                };
             }
+            self.write(w);
         }
 
-        /// In field `field_name` of this register, toggle (only) all bits that are set in `value`.
-        /// A one-field version of toggle(), more helpful if `field_name` is comptime calculated.
-        pub inline fn toggle_one(addr: *volatile Self, comptime field_name: []const u8, value: anytype) void {
-            var val = read(addr);
-            toggle_field(&val, field_name, value);
-            write(addr, val);
-        }
+        pub inline fn clear_mask(self: *volatile @This(), fields: anytype) void {
+            @setEvalBranchQuota(10_000);
+            check_type_has_all_fields(PackedT, fields);
+            const Fields = @TypeOf(fields);
 
-        /// For each `.Field = value` entry of `fields`:
-        /// In field `F` of this register, toggle (only) all bits that are set in `value`.
-        pub inline fn toggle(addr: *volatile Self, fields: anytype) void {
-            var val = read(addr);
-            inline for (@typeInfo(@TypeOf(fields)).@"struct".fields) |field| {
-                toggle_field(&val, field.name, @field(fields, field.name));
+            var w: PackedT = undefined;
+            inline for (reg_fields) |field| {
+                const access = @field(access_type, field.name);
+                @field(w, field.name) = if (@hasField(Fields, field.name))
+                    // Clear bits in this field
+                    if (access.write == .clear_mask)
+                        @field(fields, field.name)
+                    else
+                        reg_type_op_error(field.name, "clearing bits of this field by masking")
+                else switch (access.write) {
+                    // Write zeros so that nothing happens
+                    .ignored, .set_mask, .clear_mask, .toggle_mask => @field(all_zeros, field.name),
+                    else => reg_type_op_error(field.name, "clearing bits of any field in this register by masking"),
+                };
             }
-            write(addr, val);
+            self.write(w);
+        }
+
+        fn reg_type_op_error(comptime reg_name: [:0]const u8, comptime action: []const u8) noreturn {
+            const a = @field(access_type, reg_name);
+            @compileError(
+                "Register field's \"" ++ reg_name ++ "\" access type is read: " ++
+                    @tagName(a.read) ++ ", write: " ++ @tagName(a.write) ++ ",\nso " ++ action ++
+                    \\ is not possible.
+                    \\
+                    \\If you think the access type is wrong, you can add a svd patch
+                    \\in port/.../.../patches or to your build.zig directly.
+                    \\
+                    \\-freference-trace may be useful to locate where this was called.
+                ,
+            );
         }
     };
 }
diff --git a/port/espressif/esp/src/hal/clocks/esp32_c3.zig b/port/espressif/esp/src/hal/clocks/esp32_c3.zig
index 5a9eb7ca9..266178d90 100644
--- a/port/espressif/esp/src/hal/clocks/esp32_c3.zig
+++ b/port/espressif/esp/src/hal/clocks/esp32_c3.zig
@@ -153,9 +153,10 @@ fn switch_to_xtal(div: u10) void {
 }
 
 fn apb_freq_update(freq: u32) void {
+    // Why not just use the underlying register fields?
     const value = ((freq >> 12) & @as(u32, std.math.maxInt(u16))) |
         (((freq >> 12) & @as(u32, std.math.maxInt(u16))) << 16);
-    RTC_CNTL.STORE5.write_raw(value);
+    RTC_CNTL.STORE5.raw = value;
 }
 
 fn rom_cpu_frequency_update(freq: u32) void {
@@ -240,7 +241,7 @@ fn bbpll_configure(pll_freq: CpuClockSource.PllClock.PllFreq) void {
 }
 
 const I2C_ANA_MST_TYPE = extern struct {
-    ANA_CONF0: microzig.mmio.Mmio(packed struct {
+    ANA_CONF0: microzig.mmio.OldMmio(packed struct {
         reserved0: u2,
         BBPLL_STOP_FORCE_HIGH: u1,
         BBPLL_STOP_FORCE_LOW: u1,
diff --git a/port/espressif/esp/src/hal/i2c.zig b/port/espressif/esp/src/hal/i2c.zig
index 7e565df8a..f7bdf4325 100644
--- a/port/espressif/esp/src/hal/i2c.zig
+++ b/port/espressif/esp/src/hal/i2c.zig
@@ -6,7 +6,6 @@ const peripherals = microzig.chip.peripherals;
 pub const I2C0 = peripherals.I2C0;
 
 const gpio = @import("gpio.zig");
-const clocks = @import("clocks.zig");
 const time = @import("time.zig");
 
 // TODO: How and why. Is this xtal? That clock is 40_000_000 according to the hal
@@ -147,13 +146,13 @@ pub const I2C = struct {
         self.reset();
 
         // Disable all I2C interrupts
-        regs.INT_ENA.write_raw(0);
+        regs.INT_ENA.raw = 0;
 
         // Clear all I2C interrupts
         self.clear_interrupts();
 
         // Configure controller
-        regs.CTR.write_raw(0);
+        regs.CTR.raw = 0;
         regs.CTR.modify(.{
             .MS_MODE = 1, // Set I2C controller to master mode
             .SDA_FORCE_OUT = 1, // Use open drain output for SDA
@@ -236,7 +235,7 @@ pub const I2C = struct {
     fn reset_command_list(self: I2C) void {
         // Reset all command registers
         for (0..self.get_regs().COMD.len) |i|
-            self.get_regs().COMD[@intCast(i)].write_raw(0);
+            self.get_regs().COMD[@intCast(i)].raw = 0;
     }
 
     /// Set the filter threshold in clock cycles
@@ -343,7 +342,7 @@ pub const I2C = struct {
 
     /// Clear all interrupts
     inline fn clear_interrupts(self: I2C) void {
-        self.get_regs().INT_CLR.write_raw(0x3ffff);
+        self.get_regs().INT_CLR.raw = 0x3ffff;
     }
 
     inline fn start_transmission(self: I2C) void {
diff --git a/port/espressif/esp/src/hal/rng.zig b/port/espressif/esp/src/hal/rng.zig
index 5d2818d6a..adb612788 100644
--- a/port/espressif/esp/src/hal/rng.zig
+++ b/port/espressif/esp/src/hal/rng.zig
@@ -3,7 +3,7 @@ const microzig = @import("microzig");
 const RNG = microzig.chip.peripherals.RNG;
 
 pub fn random_u32() u32 {
-    return RNG.DATA;
+    return RNG.DATA.raw;
 }
 
 pub fn read(buf: []u8) void {
diff --git a/port/espressif/esp/src/hal/spi.zig b/port/espressif/esp/src/hal/spi.zig
index 2abc26370..089a375c4 100644
--- a/port/espressif/esp/src/hal/spi.zig
+++ b/port/espressif/esp/src/hal/spi.zig
@@ -32,6 +32,8 @@ pub const SPI = enum(u2) {
     _,
 
     pub const Config = struct {
+        const CLOCK = @FieldType(SPI_Regs, "CLOCK").underlying_type;
+
         clock_config: clocks.Config,
         baud_rate: u32,
         bit_order: BitOrder = .msb_first,
@@ -47,30 +49,18 @@ pub const SPI = enum(u2) {
         }
 
         // translated from esp-hal in rust
-        fn get_clock_config(self: Config) u32 {
-            // TODO: we can return directly the packed type if we add some patches
-            // to regz (not possible rn).
-            const Reg = packed struct(u32) {
-                CLKCNT_L: u6,
-                CLKCNT_H: u6,
-                CLKCNT_N: u6,
-                CLKDIV_PRE: u4,
-                reserved: u9 = 0,
-                CLK_EQU_SYSCLK: u1,
-            };
-
+        fn get_clock_config(self: Config) CLOCK {
             const source_freq = self.clock_config.apb_clk_freq;
 
             // Use APB directly if target frequency is high enough
-            if (self.baud_rate > ((source_freq / 4) * 3)) {
-                return @bitCast(@as(Reg, .{
+            if (self.baud_rate > ((source_freq / 4) * 3))
+                return .{
                     .CLKCNT_L = 0,
                     .CLKCNT_H = 0,
                     .CLKCNT_N = 0,
                     .CLKDIV_PRE = 0,
                     .CLK_EQU_SYSCLK = 1,
-                }));
-            }
+                };
 
             var bestn: i32 = -1;
             var bestpre: i32 = -1;
@@ -100,13 +90,13 @@ pub const SPI = enum(u2) {
             var h: i32 = @divFloor(128 * bestn + 127, 256);
             if (h <= 0) h = 1;
 
-            return @bitCast(@as(Reg, .{
+            return .{
                 .CLKCNT_L = @intCast(l - 1),
                 .CLKCNT_H = @intCast(h - 1),
                 .CLKCNT_N = @intCast(bestn - 1),
                 .CLKDIV_PRE = @intCast(bestpre - 1),
                 .CLK_EQU_SYSCLK = 0,
-            }));
+            };
         }
     };
 
@@ -129,7 +119,7 @@ pub const SPI = enum(u2) {
         });
 
         // this also enables using all 16 words
-        regs.USER.write_raw(0);
+        regs.USER.raw = 0;
 
         regs.CLK_GATE.modify(.{
             .MST_CLK_ACTIVE = 1,
@@ -143,11 +133,11 @@ pub const SPI = enum(u2) {
         });
 
         // this also disables all cs lines
-        regs.MISC.write_raw(0);
+        regs.MISC.raw = 0;
 
-        regs.SLAVE.write_raw(0);
+        regs.SLAVE.raw = 0;
 
-        regs.CLOCK.write_raw(config.get_clock_config());
+        regs.CLOCK.write(config.get_clock_config());
 
         regs.DMA_INT_CLR.modify(.{
             .TRANS_DONE_INT_CLR = 1,
diff --git a/port/espressif/esp/src/hal/system.zig b/port/espressif/esp/src/hal/system.zig
index a1643d8ca..831f6fc92 100644
--- a/port/espressif/esp/src/hal/system.zig
+++ b/port/espressif/esp/src/hal/system.zig
@@ -85,16 +85,16 @@ pub fn init() void {
 pub fn clocks_enable_set(mask: PeripheralMask) void {
     var current_mask: u64 = @bitCast(@as(u64, SYSTEM.PERIP_CLK_EN0.raw) | ((@as(u64, SYSTEM.PERIP_CLK_EN1.raw) << 32)));
     current_mask |= @as(u43, @bitCast(mask));
-    SYSTEM.PERIP_CLK_EN0.write_raw(@intCast(current_mask & 0xffff_ffff));
-    SYSTEM.PERIP_CLK_EN1.write_raw(@intCast(current_mask >> 32));
+    SYSTEM.PERIP_CLK_EN0.raw = @intCast(current_mask & 0xffff_ffff);
+    SYSTEM.PERIP_CLK_EN1.raw = @intCast(current_mask >> 32);
 }
 
 /// Clears the bits in the mask of the PERIP_CLK_ENx registers.
 pub fn clocks_enable_clear(mask: PeripheralMask) void {
     var current_mask: u64 = @bitCast(@as(u64, SYSTEM.PERIP_CLK_EN0.raw) | ((@as(u64, SYSTEM.PERIP_CLK_EN1.raw) << 32)));
     current_mask &= ~@as(u43, @bitCast(mask));
-    SYSTEM.PERIP_CLK_EN0.write_raw(@intCast(current_mask & 0xffff_ffff));
-    SYSTEM.PERIP_CLK_EN1.write_raw(@intCast(current_mask >> 32));
+    SYSTEM.PERIP_CLK_EN0.raw = @intCast(current_mask & 0xffff_ffff);
+    SYSTEM.PERIP_CLK_EN1.raw = @intCast(current_mask >> 32);
 }
 
 /// Sets and clears the bits in the mask of the PERIP_RST_ENx registers. Resets the peripherals.
@@ -107,16 +107,16 @@ pub fn peripheral_reset(mask: PeripheralMask) void {
 pub fn peripheral_reset_set(mask: PeripheralMask) void {
     var current_mask: u64 = @bitCast(@as(u64, SYSTEM.PERIP_RST_EN0.raw) | ((@as(u64, SYSTEM.PERIP_RST_EN1.raw) << 32)));
     current_mask |= @as(u43, @bitCast(mask));
-    SYSTEM.PERIP_RST_EN0.write_raw(@intCast(current_mask & 0xffff_ffff));
-    SYSTEM.PERIP_RST_EN1.write_raw(@intCast(current_mask >> 32));
+    SYSTEM.PERIP_RST_EN0.raw = @intCast(current_mask & 0xffff_ffff);
+    SYSTEM.PERIP_RST_EN1.raw = @intCast(current_mask >> 32);
 }
 
 /// Clears the bits in the mask of the PERIP_RST_ENx registers.
 pub fn peripheral_reset_clear(mask: PeripheralMask) void {
     var current_mask: u64 = @bitCast(@as(u64, SYSTEM.PERIP_RST_EN0.raw) | ((@as(u64, SYSTEM.PERIP_RST_EN1.raw) << 32)));
     current_mask &= ~@as(u43, @bitCast(mask));
-    SYSTEM.PERIP_RST_EN0.write_raw(@intCast(current_mask & 0xffff_ffff));
-    SYSTEM.PERIP_RST_EN1.write_raw(@intCast(current_mask >> 32));
+    SYSTEM.PERIP_RST_EN0.raw = @intCast(current_mask & 0xffff_ffff);
+    SYSTEM.PERIP_RST_EN1.raw = @intCast(current_mask >> 32);
 }
 
 /// Enable clocks and release peripherals from reset.
diff --git a/port/nordic/nrf5x/patches/nrf51.zon b/port/nordic/nrf5x/patches/nrf51.zon
index 98c6f3cc8..2f1fcb0e4 100644
--- a/port/nordic/nrf5x/patches/nrf51.zon
+++ b/port/nordic/nrf5x/patches/nrf51.zon
@@ -1,37 +1,37 @@
 .{
-    .{
-        .add_enum = .{
-            .parent = "types.peripherals.GPIO",
-            .@"enum" = .{
-                .name = "Pull",
-                .bitsize = 2,
-                .fields = .{
-                    .{ .value = 0x0, .name = "disabled" },
-                    .{ .value = 0x1, .name = "down" },
-                    .{ .value = 0x2, .name = "up" },
-                },
+    .{ .add_type_and_apply = .{
+        .parent = "types.peripherals.GPIO",
+        .type_name = "Pull",
+        .type = .{ .@"enum" = .{
+            .bitsize = 2,
+            .fields = .{
+                .{ .value = 0x0, .name = "disabled" },
+                .{ .value = 0x1, .name = "down" },
+                .{ .value = 0x2, .name = "up" },
             },
+        } },
+        .apply_to = .{
+            "types.peripherals.GPIO.PIN_CNF.PULL",
         },
-    },
-    .{ .set_enum_type = .{ .of = "types.peripherals.GPIO.PIN_CNF.PULL", .to = "types.peripherals.GPIO.Pull" } },
-    .{
-        .add_enum = .{
-            .parent = "types.peripherals.GPIO",
-            .@"enum" = .{
-                .name = "DriveStrength",
-                .bitsize = 3,
-                .fields = .{
-                    .{ .value = 0x0, .name = "SOS1" },
-                    .{ .value = 0x1, .name = "HOS1" },
-                    .{ .value = 0x2, .name = "SOH1" },
-                    .{ .value = 0x3, .name = "HOH1" },
-                    .{ .value = 0x4, .name = "DOS1" },
-                    .{ .value = 0x5, .name = "DOH1" },
-                    .{ .value = 0x6, .name = "SOD1" },
-                    .{ .value = 0x7, .name = "HOD1" },
-                },
+    } },
+    .{ .add_type_and_apply = .{
+        .parent = "types.peripherals.GPIO",
+        .type_name = "DriveStrength",
+        .type = .{ .@"enum" = .{
+            .bitsize = 3,
+            .fields = .{
+                .{ .value = 0x0, .name = "SOS1" },
+                .{ .value = 0x1, .name = "HOS1" },
+                .{ .value = 0x2, .name = "SOH1" },
+                .{ .value = 0x3, .name = "HOH1" },
+                .{ .value = 0x4, .name = "DOS1" },
+                .{ .value = 0x5, .name = "DOH1" },
+                .{ .value = 0x6, .name = "SOD1" },
+                .{ .value = 0x7, .name = "HOD1" },
             },
+        } },
+        .apply_to = .{
+            "types.peripherals.GPIO.PIN_CNF.DRIVE",
         },
-    },
-    .{ .set_enum_type = .{ .of = "types.peripherals.GPIO.PIN_CNF.DRIVE", .to = "types.peripherals.GPIO.DriveStrength" } },
+    } },
 }
diff --git a/port/nordic/nrf5x/patches/nrf528xx.zon b/port/nordic/nrf5x/patches/nrf528xx.zon
index f7cdd28e9..3f2b7e6db 100644
--- a/port/nordic/nrf5x/patches/nrf528xx.zon
+++ b/port/nordic/nrf5x/patches/nrf528xx.zon
@@ -1,37 +1,37 @@
 .{
-    .{
-        .add_enum = .{
-            .parent = "types.peripherals.P0",
-            .@"enum" = .{
-                .name = "Pull",
-                .bitsize = 2,
-                .fields = .{
-                    .{ .value = 0x0, .name = "disabled" },
-                    .{ .value = 0x1, .name = "down" },
-                    .{ .value = 0x2, .name = "up" },
-                },
+    .{ .add_type_and_apply = .{
+        .parent = "types.peripherals.P0",
+        .type_name = "Pull",
+        .type = .{ .@"enum" = .{
+            .bitsize = 2,
+            .fields = .{
+                .{ .value = 0x0, .name = "disabled" },
+                .{ .value = 0x1, .name = "down" },
+                .{ .value = 0x2, .name = "up" },
             },
+        } },
+        .apply_to = .{
+            "types.peripherals.P0.PIN_CNF.PULL",
         },
-    },
-    .{ .set_enum_type = .{ .of = "types.peripherals.P0.PIN_CNF.PULL", .to = "types.peripherals.P0.Pull" } },
-    .{
-        .add_enum = .{
-            .parent = "types.peripherals.P0",
-            .@"enum" = .{
-                .name = "DriveStrength",
-                .bitsize = 3,
-                .fields = .{
-                    .{ .value = 0x0, .name = "SOS1" },
-                    .{ .value = 0x1, .name = "HOS1" },
-                    .{ .value = 0x2, .name = "SOH1" },
-                    .{ .value = 0x3, .name = "HOH1" },
-                    .{ .value = 0x4, .name = "DOS1" },
-                    .{ .value = 0x5, .name = "DOH1" },
-                    .{ .value = 0x6, .name = "SOD1" },
-                    .{ .value = 0x7, .name = "HOD1" },
-                },
+    } },
+    .{ .add_type_and_apply = .{
+        .parent = "types.peripherals.P0",
+        .type_name = "DriveStrength",
+        .type = .{ .@"enum" = .{
+            .bitsize = 3,
+            .fields = .{
+                .{ .value = 0x0, .name = "SOS1" },
+                .{ .value = 0x1, .name = "HOS1" },
+                .{ .value = 0x2, .name = "SOH1" },
+                .{ .value = 0x3, .name = "HOH1" },
+                .{ .value = 0x4, .name = "DOS1" },
+                .{ .value = 0x5, .name = "DOH1" },
+                .{ .value = 0x6, .name = "SOD1" },
+                .{ .value = 0x7, .name = "HOD1" },
             },
+        } },
+        .apply_to = .{
+            "types.peripherals.P0.PIN_CNF.DRIVE",
         },
-    },
-    .{ .set_enum_type = .{ .of = "types.peripherals.P0.PIN_CNF.DRIVE", .to = "types.peripherals.P0.DriveStrength" } },
+    } },
 }
diff --git a/port/nordic/nrf5x/src/hal/clocks.zig b/port/nordic/nrf5x/src/hal/clocks.zig
index cbddea02d..10498cdc9 100644
--- a/port/nordic/nrf5x/src/hal/clocks.zig
+++ b/port/nordic/nrf5x/src/hal/clocks.zig
@@ -1,5 +1,3 @@
-const std = @import("std");
-
 const microzig = @import("microzig");
 const CLOCK = microzig.chip.peripherals.CLOCK;
 
@@ -16,27 +14,12 @@ const version: enum {
 
 pub const hfxo = struct {
     pub fn start() void {
-        switch (version) {
-            .nrf51 => {
-                CLOCK.TASKS_HFCLKSTART = 1;
-                while (CLOCK.EVENTS_HFCLKSTARTED == 0) {}
-            },
-            .nrf52 => {
-                CLOCK.TASKS_HFCLKSTART.write_raw(1);
-                while (CLOCK.EVENTS_HFCLKSTARTED.raw == 0) {}
-            },
-        }
+        CLOCK.TASKS_HFCLKSTART.raw = 1;
+        while (CLOCK.EVENTS_HFCLKSTARTED.raw == 0) {}
     }
 
     pub fn stop() void {
-        switch (version) {
-            .nrf51 => {
-                CLOCK.TASKS_HFCLKSTOP = 1;
-            },
-            .nrf52 => {
-                CLOCK.TASKS_HFCLKSTOP.write_raw(1);
-            },
-        }
+        CLOCK.TASKS_HFCLKSTOP.raw = 1;
     }
 };
 
@@ -63,16 +46,8 @@ pub const lfclk = struct {
     };
 
     pub fn calibrate() void {
-        switch (version) {
-            .nrf51 => {
-                CLOCK.TASKS_CAL = 1;
-                while (CLOCK.EVENTS_DONE == 0) {}
-            },
-            .nrf52 => {
-                CLOCK.TASKS_CAL.write_raw(1);
-                while (CLOCK.EVENTS_DONE.raw == 0) {}
-            },
-        }
+        CLOCK.TASKS_CAL.raw = 1;
+        while (CLOCK.EVENTS_DONE.raw == 0) {}
     }
 
     pub fn set_source(comptime source: Source) void {
@@ -131,26 +106,11 @@ pub const lfclk = struct {
     }
 
     pub fn start() void {
-        switch (version) {
-            .nrf51 => {
-                CLOCK.TASKS_LFCLKSTART = 1;
-                while (CLOCK.EVENTS_LFCLKSTARTED == 0) {}
-            },
-            .nrf52 => {
-                CLOCK.TASKS_LFCLKSTART.write_raw(1);
-                while (CLOCK.EVENTS_LFCLKSTARTED.raw == 0) {}
-            },
-        }
+        CLOCK.TASKS_LFCLKSTART.raw = 1;
+        while (CLOCK.EVENTS_LFCLKSTARTED.raw == 0) {}
     }
 
     pub fn stop() void {
-        switch (version) {
-            .nrf51 => {
-                CLOCK.TASKS_LFCLKSTOP = 1;
-            },
-            .nrf52 => {
-                CLOCK.TASKS_LFCLKSTOP.write_raw(1);
-            },
-        }
+        CLOCK.TASKS_LFCLKSTOP.raw = 1;
     }
 };
diff --git a/port/nordic/nrf5x/src/hal/spim.zig b/port/nordic/nrf5x/src/hal/spim.zig
index f410a26bc..2cf2aa768 100644
--- a/port/nordic/nrf5x/src/hal/spim.zig
+++ b/port/nordic/nrf5x/src/hal/spim.zig
@@ -22,8 +22,8 @@ const version: enum {
 
 const SPIM0 = peripherals.SPIM0;
 const SPIM1 = peripherals.SPIM1;
-const SPIM2 = peripherals.SPIM2;
-const SPIM3 = peripherals.SPIM3;
+// const SPIM2 = peripherals.SPIM2;
+// const SPIM3 = peripherals.SPIM3;
 
 const SpimRegs = microzig.chip.types.peripherals.SPIM0;
 
@@ -174,7 +174,7 @@ pub const SPIM = enum(u1) {
         }
 
         regs.ENABLE.write(.{ .ENABLE = .Enabled });
-        regs.INTENCLR.write_raw(0xFFFFFFFF);
+        regs.INTENCLR.raw = 0xFFFF_FFFF;
     }
 
     pub fn write_blocking(spi: SPIM, data: []const u8, timeout: ?Duration) TransactionError!void {
@@ -240,10 +240,10 @@ pub const SPIM = enum(u1) {
 
     fn prepare_dma_transfer(spi: SPIM, tx: []const u8, rx: []u8) TransactionError!void {
         const regs = spi.get_regs();
-        regs.RXD.PTR.write_raw(@intFromPtr(rx.ptr));
+        regs.RXD.PTR.raw = @intFromPtr(rx.ptr);
         regs.RXD.MAXCNT.write(.{ .MAXCNT = @truncate(rx.len) });
 
-        regs.TXD.PTR.write_raw(@intFromPtr(tx.ptr));
+        regs.TXD.PTR.raw = @intFromPtr(tx.ptr);
         regs.TXD.MAXCNT.write(.{ .MAXCNT = @truncate(tx.len) });
 
         regs.EVENTS_END.write(.{ .EVENTS_END = .NotGenerated });
diff --git a/port/nordic/nrf5x/src/hal/time.zig b/port/nordic/nrf5x/src/hal/time.zig
index f1f8ea0c0..02e4f4ba7 100644
--- a/port/nordic/nrf5x/src/hal/time.zig
+++ b/port/nordic/nrf5x/src/hal/time.zig
@@ -10,15 +10,6 @@ const time = microzig.drivers.time;
 const clocks = microzig.hal.clocks;
 const compatibility = microzig.hal.compatibility;
 
-const version: enum {
-    nrf51,
-    nrf52,
-} = switch (compatibility.chip) {
-    .nrf51 => .nrf51,
-    .nrf52, .nrf52833, .nrf52840 => .nrf52,
-    else => compatibility.unsupported_chip("time"),
-};
-
 const rtc = microzig.chip.peripherals.RTC0;
 const COMPARE_INDEX = 2;
 const TIMER_BITS = 23;
@@ -51,16 +42,8 @@ pub fn init() void {
     rtc.CC[COMPARE_INDEX].write(.{ .COMPARE = 0x800000 });
 
     // Clear counter, then start timer
-    switch (version) {
-        .nrf51 => {
-            rtc.TASKS_CLEAR = 1;
-            rtc.TASKS_START = 1;
-        },
-        .nrf52 => {
-            rtc.TASKS_CLEAR.write_raw(1);
-            rtc.TASKS_START.write_raw(1);
-        },
-    }
+    rtc.TASKS_CLEAR.raw = 1;
+    rtc.TASKS_START.raw = 1;
 
     // Wait for clear
     while (rtc.COUNTER.read().COUNTER != 0) {}
@@ -69,29 +52,14 @@ pub fn init() void {
 /// Handle both overflow and compare interrupts. Update the period which acts as the high bits of
 /// the elapsed time.
 pub fn rtc_interrupt() callconv(.c) void {
-    switch (version) {
-        .nrf51 => {
-            if (rtc.EVENTS_OVRFLW == 1) {
-                rtc.EVENTS_OVRFLW = 0;
-                next_period();
-            }
-
-            if (rtc.EVENTS_COMPARE[COMPARE_INDEX] == 1) {
-                rtc.EVENTS_COMPARE[COMPARE_INDEX] = 0;
-                next_period();
-            }
-        },
-        .nrf52 => {
-            if (rtc.EVENTS_OVRFLW.raw == 1) {
-                rtc.EVENTS_OVRFLW.write_raw(0);
-                next_period();
-            }
-
-            if (rtc.EVENTS_COMPARE[COMPARE_INDEX].raw == 1) {
-                rtc.EVENTS_COMPARE[COMPARE_INDEX].write_raw(0);
-                next_period();
-            }
-        },
+    if (rtc.EVENTS_OVRFLW.raw == 1) {
+        rtc.EVENTS_OVRFLW.raw = 0;
+        next_period();
+    }
+
+    if (rtc.EVENTS_COMPARE[COMPARE_INDEX].raw == 1) {
+        rtc.EVENTS_COMPARE[COMPARE_INDEX].raw = 0;
+        next_period();
     }
 }
 
diff --git a/port/nxp/mcx/src/mcxa153/hal/gpio.zig b/port/nxp/mcx/src/mcxa153/hal/gpio.zig
index 8e50b97b6..600ef8022 100644
--- a/port/nxp/mcx/src/mcxa153/hal/gpio.zig
+++ b/port/nxp/mcx/src/mcxa153/hal/gpio.zig
@@ -27,7 +27,7 @@ pub const GPIO = enum(u7) {
         const old: u32 = regs.PDOR.raw;
         const new = @as(u32, output) << gpio.get_pin();
 
-        regs.PDOR.write_raw(old & ~gpio.get_mask() | new);
+        regs.PDOR.raw = old & ~gpio.get_mask() | new;
     }
 
     pub fn get(gpio: GPIO) bool {
@@ -40,7 +40,7 @@ pub const GPIO = enum(u7) {
         const regs = gpio.get_regs();
         const old: u32 = regs.PTOR.raw;
 
-        regs.PTOR.write_raw(old | gpio.get_mask());
+        regs.PTOR.raw = old | gpio.get_mask();
     }
 
     pub fn set_direction(gpio: GPIO, direction: Direction) void {
@@ -48,7 +48,7 @@ pub const GPIO = enum(u7) {
         const old: u32 = regs.PDDR.raw;
         const new = @as(u32, @intFromEnum(direction)) << gpio.get_pin();
 
-        regs.PDDR.write_raw(old & ~gpio.get_mask() | new);
+        regs.PDDR.raw = old & ~gpio.get_mask() | new;
     }
 
     pub fn set_interrupt_config(gpio: GPIO, trigger: InterruptConfig) void {
@@ -56,7 +56,7 @@ pub const GPIO = enum(u7) {
         const irqc = @as(u32, @intFromEnum(trigger)) << 16;
         const isf = @as(u32, 1) << 24;
 
-        regs.ICR[gpio.get_pin()].write_raw(irqc | isf);
+        regs.ICR[gpio.get_pin()].raw = irqc | isf;
     }
 
     pub fn get_interrupt_flag(gpio: GPIO) bool {
@@ -69,7 +69,7 @@ pub const GPIO = enum(u7) {
         const regs = gpio.get_regs();
         const old: u32 = regs.ISFR0.raw;
 
-        regs.ISFR0.write_raw(old | gpio.get_mask());
+        regs.ISFR0.raw = old | gpio.get_mask();
     }
 
     fn get_regs(gpio: GPIO) *volatile chip.types.peripherals.GPIO0 {
diff --git a/port/nxp/mcx/src/mcxa153/hal/syscon.zig b/port/nxp/mcx/src/mcxa153/hal/syscon.zig
index 82f56c532..e4a168694 100644
--- a/port/nxp/mcx/src/mcxa153/hal/syscon.zig
+++ b/port/nxp/mcx/src/mcxa153/hal/syscon.zig
@@ -15,12 +15,11 @@ pub fn enable_clock(comptime peripheral: Peripheral) void {
     defer freeze_clock_configuration();
 
     switch (peripheral.cc()) {
-        0 => chip.peripherals.MRCC0.MRCC_GLB_CC0_SET.write_raw(
+        0 => chip.peripherals.MRCC0.MRCC_GLB_CC0_SET.raw =
             @as(u32, @bitCast(chip.peripherals.MRCC0.MRCC_GLB_CC0_SET)) | peripheral.mask(),
-        ),
-        1 => chip.peripherals.MRCC0.MRCC_GLB_CC1_SET.write_raw(
+
+        1 => chip.peripherals.MRCC0.MRCC_GLB_CC1_SET.raw =
             @as(u32, @bitCast(chip.peripherals.MRCC0.MRCC_GLB_CC1_SET)) | peripheral.mask(),
-        ),
     }
 }
 
@@ -29,12 +28,11 @@ pub fn disable_clock(comptime peripheral: Peripheral) void {
     defer freeze_clock_configuration();
 
     switch (peripheral.cc()) {
-        0 => chip.peripherals.MRCC0.MRCC_GLB_CC0_CLR.write_raw(
+        0 => chip.peripherals.MRCC0.MRCC_GLB_CC0_CLR.raw =
             @as(u32, @bitCast(chip.peripherals.MRCC0.MRCC_GLB_CC0_CLR)) | peripheral.mask(),
-        ),
-        1 => chip.peripherals.MRCC0.MRCC_GLB_CC1_CLR.write_raw(
+
+        1 => chip.peripherals.MRCC0.MRCC_GLB_CC1_CLR.raw =
             @as(u32, @bitCast(chip.peripherals.MRCC0.MRCC_GLB_CC1_CLR)) | peripheral.mask(),
-        ),
     }
 }
 
@@ -43,12 +41,11 @@ pub fn reset_release(comptime peripheral: Peripheral) void {
     defer freeze_clock_configuration();
 
     switch (peripheral.cc()) {
-        0 => chip.peripherals.MRCC0.MRCC_GLB_RST0_SET.write_raw(
+        0 => chip.peripherals.MRCC0.MRCC_GLB_RST0_SET.raw =
             @as(u32, @bitCast(chip.peripherals.MRCC0.MRCC_GLB_RST0_SET)) | peripheral.mask(),
-        ),
-        1 => chip.peripherals.MRCC0.MRCC_GLB_RST1_SET.write_raw(
+
+        1 => chip.peripherals.MRCC0.MRCC_GLB_RST1_SET.raw =
             @as(u32, @bitCast(chip.peripherals.MRCC0.MRCC_GLB_RST1_SET)) | peripheral.mask(),
-        ),
     }
 }
 
@@ -57,12 +54,11 @@ pub fn reset_assert(comptime peripheral: Peripheral) void {
     defer freeze_clock_configuration();
 
     switch (peripheral.cc()) {
-        0 => chip.peripherals.MRCC0.MRCC_GLB_RST0_CLR.write_raw(
+        0 => chip.peripherals.MRCC0.MRCC_GLB_RST0_CLR.raw =
             @as(u32, @bitCast(chip.peripherals.MRCC0.MRCC_GLB_RST0_CLR)) | peripheral.mask(),
-        ),
-        1 => chip.peripherals.MRCC0.MRCC_GLB_RST1_CLR.write_raw(
+
+        1 => chip.peripherals.MRCC0.MRCC_GLB_RST1_CLR.raw =
             @as(u32, @bitCast(chip.peripherals.MRCC0.MRCC_GLB_RST1_CLR)) | peripheral.mask(),
-        ),
     }
 }
 
diff --git a/port/nxp/mcx/src/mcxn947/hal/flexcomm/LP_I2C.zig b/port/nxp/mcx/src/mcxn947/hal/flexcomm/LP_I2C.zig
index 9c74160d3..acae9659a 100644
--- a/port/nxp/mcx/src/mcxn947/hal/flexcomm/LP_I2C.zig
+++ b/port/nxp/mcx/src/mcxn947/hal/flexcomm/LP_I2C.zig
@@ -147,7 +147,7 @@ pub const LP_I2C = enum(u4) {
     }
 
     pub fn clear_flags(i2c: LP_I2C) void {
-        i2c.get_regs().MSR.write_raw(0);
+        i2c.get_regs().MSR.raw = 0;
     }
 
     fn reset_fifos(i2c: LP_I2C) void {
@@ -369,7 +369,8 @@ pub const LP_I2C = enum(u4) {
             flags = i2c.get_regs().MSR.read();
             try i2c.check_flags();
         }
-        i2c.get_regs().MSR.write_raw(1 << 9);
+        // Why nut use the underlying struct?
+        i2c.get_regs().MSR.raw = 1 << 9;
     }
 
     fn wait_for_tx_space(i2c: LP_I2C) Error!void {
diff --git a/port/nxp/mcx/src/mcxn947/hal/flexcomm/LP_UART.zig b/port/nxp/mcx/src/mcxn947/hal/flexcomm/LP_UART.zig
index 592eac7b9..346299d02 100644
--- a/port/nxp/mcx/src/mcxn947/hal/flexcomm/LP_UART.zig
+++ b/port/nxp/mcx/src/mcxn947/hal/flexcomm/LP_UART.zig
@@ -90,7 +90,7 @@ pub const LP_UART = enum(u4) {
 
         stat.MSBF = if (config.bit_order == .lsb) .LSB_FIRST else .MSB_FIRST;
         stat.RXINV = if (config.rx_invert) .INVERTED else .NOT_INVERTED;
-        regs.STAT.modify(stat);
+        regs.STAT.write(stat);
 
         uart.set_enabled(config.enable_send, config.enable_receive);
 
diff --git a/port/nxp/mcx/src/mcxn947/hal/gpio.zig b/port/nxp/mcx/src/mcxn947/hal/gpio.zig
index dce1d4e95..58a9986c0 100644
--- a/port/nxp/mcx/src/mcxn947/hal/gpio.zig
+++ b/port/nxp/mcx/src/mcxn947/hal/gpio.zig
@@ -33,9 +33,9 @@ pub const GPIO = enum(u8) {
 
         const new: u32 = @as(u32, 1) << gpio.get_pin();
         if (output == 1)
-            regs.PSOR.write_raw(new)
+            regs.PSOR.raw = new
         else
-            regs.PCOR.write_raw(new);
+            regs.PCOR.raw = new;
     }
 
     /// Returns the logical input of the GPIO.
@@ -49,7 +49,7 @@ pub const GPIO = enum(u8) {
     pub fn toggle(gpio: GPIO) void {
         const regs = gpio.get_regs();
 
-        regs.PTOR.write_raw(gpio.get_mask());
+        regs.PTOR.raw = gpio.get_mask();
     }
 
     pub fn set_direction(gpio: GPIO, direction: Direction) void {
@@ -57,7 +57,7 @@ pub const GPIO = enum(u8) {
         const old: u32 = regs.PDDR.raw;
         const new = @as(u32, @intFromEnum(direction)) << gpio.get_pin();
 
-        regs.PDDR.write_raw((old & ~gpio.get_mask()) | new);
+        regs.PDDR.raw = (old & ~gpio.get_mask()) | new;
     }
 
     /// Returns the gpio's control register
diff --git a/port/nxp/mcx/src/mcxn947/hal/pin.zig b/port/nxp/mcx/src/mcxn947/hal/pin.zig
index 93c141e90..abd3da96d 100644
--- a/port/nxp/mcx/src/mcxn947/hal/pin.zig
+++ b/port/nxp/mcx/src/mcxn947/hal/pin.zig
@@ -36,7 +36,7 @@ pub const Pin = enum(u8) {
         const base = @intFromPtr(&pin.get_port().get_regs().PCR0);
         const reg: PinTy = @ptrFromInt(base + pin.get_n() * @as(u32, 4));
 
-        reg.write_raw(@as(u16, @bitCast(config)));
+        reg.raw = @as(u16, @bitCast(config));
     }
 
     /// Returns the pin configurator (essentially a builder).
diff --git a/port/nxp/mcx/src/mcxn947/hal/syscon.zig b/port/nxp/mcx/src/mcxn947/hal/syscon.zig
index 22f4afaf8..5d28526ce 100644
--- a/port/nxp/mcx/src/mcxn947/hal/syscon.zig
+++ b/port/nxp/mcx/src/mcxn947/hal/syscon.zig
@@ -1,4 +1,3 @@
-const std = @import("std");
 const microzig = @import("microzig");
 const chip = microzig.chip;
 
@@ -18,7 +17,7 @@ pub fn module_enable_clock(module: Module) void {
     if (!module.can_control_clock()) return;
 
     const reg = &chip.peripherals.SYSCON0.AHBCLKCTRLSET[module.cc()];
-    reg.write_raw(@as(u32, 1) << module.offset());
+    reg.raw = @as(u32, 1) << module.offset();
 }
 
 /// Disables the module's clock.
@@ -27,7 +26,7 @@ pub fn module_disable_clock(module: Module) void {
     if (!module.can_control_clock()) return;
 
     const reg = &chip.peripherals.SYSCON0.AHBCLKCTRLCLR[module.cc()];
-    reg.write_raw(@as(u32, 1) << module.offset());
+    reg.raw = @as(u32, 1) << module.offset();
 }
 
 // same as for `module_enable_clock`
@@ -38,7 +37,7 @@ pub fn module_reset_assert(module: Module) void {
     if (!module.can_reset()) return;
 
     const reg = &chip.peripherals.SYSCON0.PRESETCTRLSET[module.cc()];
-    reg.write_raw(@as(u32, 1) << module.offset());
+    reg.raw = @as(u32, 1) << module.offset();
 }
 
 /// Release the module's reset.
@@ -47,7 +46,7 @@ pub fn module_reset_release(module: Module) void {
     if (!module.can_reset()) return;
 
     const reg = &chip.peripherals.SYSCON0.PRESETCTRLCLR[module.cc()];
-    reg.write_raw(@as(u32, 1) << module.offset());
+    reg.raw = @as(u32, 1) << module.offset();
 }
 
 // This enum can be automatically generated using `generate.zig`,
diff --git a/port/raspberrypi/rp2xxx/patches/rp2040.zon b/port/raspberrypi/rp2xxx/patches/rp2040.zon
index 75af11c9e..f2e73bbe1 100644
--- a/port/raspberrypi/rp2xxx/patches/rp2040.zon
+++ b/port/raspberrypi/rp2xxx/patches/rp2040.zon
@@ -1,8 +1,195 @@
 .{
-    .{ .add_enum_and_apply = .{
+    .{ .add_type_and_apply = .{
+        .parent = "types.peripherals.IO_BANK0",
+        .type_name = "Override",
+        .type = .{ .@"enum" = .{
+            .bitsize = 2,
+            .fields = .{
+                .{ .value = 0, .name = "normal" },
+                .{ .value = 1, .name = "invert" },
+                .{ .value = 2, .name = "low" },
+                .{ .value = 3, .name = "high" },
+            },
+        } },
+        .apply_to = .{
+            "types.peripherals.IO_BANK0.GPIO0_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO0_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO0_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO0_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO1_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO1_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO1_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO1_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO2_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO2_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO2_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO2_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO3_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO3_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO3_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO3_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO4_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO4_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO4_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO4_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO5_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO5_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO5_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO5_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO6_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO6_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO6_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO6_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO7_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO7_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO7_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO7_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO8_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO8_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO8_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO8_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO9_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO9_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO9_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO9_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO10_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO10_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO10_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO10_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO11_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO11_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO11_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO11_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO12_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO12_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO12_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO12_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO13_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO13_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO13_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO13_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO14_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO14_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO14_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO14_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO15_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO15_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO15_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO15_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO16_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO16_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO16_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO16_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO17_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO17_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO17_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO17_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO18_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO18_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO18_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO18_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO19_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO19_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO19_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO19_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO20_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO20_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO20_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO20_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO21_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO21_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO21_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO21_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO22_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO22_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO22_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO22_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO23_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO23_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO23_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO23_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO24_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO24_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO24_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO24_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO25_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO25_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO25_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO25_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO26_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO26_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO26_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO26_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO27_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO27_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO27_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO27_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO28_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO28_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO28_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO28_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO29_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO29_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO29_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO29_CTRL.OUTOVER",
+        },
+    } },
+    .{ .add_type_and_apply = .{
+        .parent = "types.peripherals.IO_BANK0",
+        .type_name = "Function",
+        .type = .{ .@"enum" = .{
+            .bitsize = 5,
+            .fields = .{
+                .{ .value = 0, .name = "xip" },
+                .{ .value = 1, .name = "spi" },
+                .{ .value = 2, .name = "uart" },
+                .{ .value = 3, .name = "i2c" },
+                .{ .value = 4, .name = "pwm" },
+                .{ .value = 5, .name = "sio" },
+                .{ .value = 6, .name = "pio0" },
+                .{ .value = 7, .name = "pio1" },
+                .{ .value = 8, .name = "gpck" },
+                .{ .value = 9, .name = "usb" },
+                .{ .value = 0x1f, .name = "disabled" },
+            },
+        } },
+        .apply_to = .{
+            "types.peripherals.IO_BANK0.GPIO0_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO1_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO2_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO3_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO4_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO5_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO6_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO7_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO8_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO9_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO10_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO11_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO12_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO13_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO14_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO15_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO16_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO17_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO18_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO19_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO20_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO21_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO22_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO23_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO24_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO25_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO26_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO27_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO28_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO29_CTRL.FUNCSEL",
+        },
+    } },
+    .{ .add_type_and_apply = .{
         .parent = "types.peripherals.USB_DPRAM",
-        .@"enum" = .{
-            .name = "EndpointType",
+        .type_name = "EndpointType",
+        .type = .{ .@"enum" = .{
             .bitsize = 2,
             .fields = .{
                 .{ .name = "control", .value = 0 },
@@ -10,7 +197,7 @@
                 .{ .name = "bulk", .value = 2 },
                 .{ .name = "interrupt", .value = 3 },
             },
-        },
+        } },
         .apply_to = .{
             "types.peripherals.USB_DPRAM.EP1_IN_CONTROL.ENDPOINT_TYPE",
             "types.peripherals.USB_DPRAM.EP1_OUT_CONTROL.ENDPOINT_TYPE",
@@ -44,17 +231,17 @@
             "types.peripherals.USB_DPRAM.EP15_OUT_CONTROL.ENDPOINT_TYPE",
         },
     } },
-    .{ .add_enum_and_apply = .{
+    .{ .add_type_and_apply = .{
         .parent = "types.peripherals.DMA",
-        .@"enum" = .{
-            .name = "DataSize",
+        .type_name = "DataSize",
+        .type = .{ .@"enum" = .{
             .bitsize = 2,
             .fields = .{
                 .{ .name = "size_8", .value = 0 },
                 .{ .name = "size_16", .value = 1 },
                 .{ .name = "size_32", .value = 2 },
             },
-        },
+        } },
         .apply_to = .{
             "types.peripherals.DMA.CH0_CTRL_TRIG.DATA_SIZE",
             "types.peripherals.DMA.CH1_CTRL_TRIG.DATA_SIZE",
@@ -70,10 +257,10 @@
             "types.peripherals.DMA.CH11_CTRL_TRIG.DATA_SIZE",
         },
     } },
-    .{ .add_enum_and_apply = .{
+    .{ .add_type_and_apply = .{
         .parent = "types.peripherals.DMA",
-        .@"enum" = .{
-            .name = "Dreq",
+        .type_name = "Dreq",
+        .type = .{ .@"enum" = .{
             .bitsize = 6,
             .fields = .{
                 .{ .name = "pio0_tx0", .value = 0 },
@@ -122,7 +309,7 @@
                 .{ .name = "timer3", .value = 62 },
                 .{ .name = "permanent", .value = 63 },
             },
-        },
+        } },
         .apply_to = .{
             "types.peripherals.DMA.CH0_CTRL_TRIG.TREQ_SEL",
             "types.peripherals.DMA.CH1_CTRL_TRIG.TREQ_SEL",
@@ -138,10 +325,10 @@
             "types.peripherals.DMA.CH11_CTRL_TRIG.TREQ_SEL",
         },
     } },
-    .{ .add_enum_and_apply = .{
+    .{ .add_type_and_apply = .{
         .parent = "types.peripherals.USB_DPRAM",
-        .@"enum" = .{
-            .name = "BufferOffset",
+        .type_name = "BufferOffset",
+        .type = .{ .@"enum" = .{
             .bitsize = 2,
             .fields = .{
                 .{ .name = "128", .value = 0 },
@@ -149,7 +336,7 @@
                 .{ .name = "512", .value = 2 },
                 .{ .name = "1024", .value = 3 },
             },
-        },
+        } },
         .apply_to = .{
             "types.peripherals.USB_DPRAM.EP0_IN_BUFFER_CONTROL.DOUBLE_BUFFER_ISO_OFFSET",
             "types.peripherals.USB_DPRAM.EP0_OUT_BUFFER_CONTROL.DOUBLE_BUFFER_ISO_OFFSET",
@@ -185,19 +372,19 @@
             "types.peripherals.USB_DPRAM.EP15_OUT_BUFFER_CONTROL.DOUBLE_BUFFER_ISO_OFFSET",
         },
     } },
-    .{ .add_enum_and_apply = .{
+    .{ .add_type_and_apply = .{
         .parent = "types.peripherals.ROSC",
-        .@"enum" = .{
-            .name = "Password",
+        .type_name = "Password",
+        .type = .{ .@"enum" = .{
             .bitsize = 16,
             .fields = .{.{ .name = "PASS", .value = 38550 }},
-        },
+        } },
         .apply_to = .{ "types.peripherals.ROSC.FREQA.PASSWD", "types.peripherals.ROSC.FREQB.PASSWD" },
     } },
-    .{ .add_enum_and_apply = .{
+    .{ .add_type_and_apply = .{
         .parent = "types.peripherals.PWM",
-        .@"enum" = .{
-            .name = "DivMode",
+        .type_name = "DivMode",
+        .type = .{ .@"enum" = .{
             .bitsize = 2,
             .fields = .{
                 .{
@@ -221,7 +408,7 @@
                     .value = 3,
                 },
             },
-        },
+        } },
         .apply_to = .{
             "types.peripherals.PWM.CH0_CSR.DIVMODE",
             "types.peripherals.PWM.CH1_CSR.DIVMODE",
@@ -233,10 +420,10 @@
             "types.peripherals.PWM.CH7_CSR.DIVMODE",
         },
     } },
-    .{ .add_enum_and_apply = .{
+    .{ .add_type_and_apply = .{
         .parent = "types.peripherals.PIO0",
-        .@"enum" = .{
-            .name = "StatusSelect",
+        .type_name = "StatusSelect",
+        .type = .{ .@"enum" = .{
             .bitsize = 1,
             .fields = .{ .{
                 .name = "TXLEVEL",
@@ -247,7 +434,7 @@
                 .description = "All-ones if RX FIFO level < N, otherwise all-zeroes",
                 .value = 1,
             } },
-        },
+        } },
         .apply_to = .{
             "types.peripherals.PIO0.SM0_EXECCTRL.STATUS_SEL",
             "types.peripherals.PIO0.SM1_EXECCTRL.STATUS_SEL",
@@ -255,10 +442,10 @@
             "types.peripherals.PIO0.SM3_EXECCTRL.STATUS_SEL",
         },
     } },
-    .{ .add_enum_and_apply = .{
+    .{ .add_type_and_apply = .{
         .parent = "types.peripherals.I2C0",
-        .@"enum" = .{
-            .name = "RxUnderState",
+        .type_name = "RxUnderState",
+        .type = .{ .@"enum" = .{
             .bitsize = 1,
             .fields = .{ .{
                 .name = "INACTIVE",
@@ -269,16 +456,16 @@
                 .description = "RX_UNDER interrupt is active",
                 .value = 1,
             } },
-        },
+        } },
         .apply_to = .{ "types.peripherals.I2C0.IC_INTR_STAT.R_RX_UNDER", "types.peripherals.I2C0.IC_RAW_INTR_STAT.RX_UNDER" },
     } },
-    .{ .add_enum_and_apply = .{
+    .{ .add_type_and_apply = .{
         .parent = "types.peripherals.DMA",
-        .@"enum" = .{
-            .name = "RingSize",
+        .type_name = "RingSize",
+        .type = .{ .@"enum" = .{
             .bitsize = 4,
             .fields = .{.{ .name = "RING_NONE", .value = 0 }},
-        },
+        } },
         .apply_to = .{
             "types.peripherals.DMA.CH0_CTRL_TRIG.RING_SIZE",
             "types.peripherals.DMA.CH1_CTRL_TRIG.RING_SIZE",
@@ -294,10 +481,10 @@
             "types.peripherals.DMA.CH11_CTRL_TRIG.RING_SIZE",
         },
     } },
-    .{ .add_enum_and_apply = .{
+    .{ .add_type_and_apply = .{
         .parent = "types.peripherals.CLOCKS",
-        .@"enum" = .{
-            .name = "AuxSrc",
+        .type_name = "AuxSrc",
+        .type = .{ .@"enum" = .{
             .bitsize = 4,
             .fields = .{
                 .{ .name = "clksrc_pll_sys", .value = 0 },
@@ -312,13 +499,13 @@
                 .{ .name = "clk_rtc", .value = 9 },
                 .{ .name = "clk_ref", .value = 10 },
             },
-        },
+        } },
         .apply_to = .{ "types.peripherals.CLOCKS.CLK_GPOUT0_CTRL.AUXSRC", "types.peripherals.CLOCKS.CLK_GPOUT1_CTRL.AUXSRC" },
     } },
-    .{ .add_enum_and_apply = .{
+    .{ .add_type_and_apply = .{
         .parent = "types.peripherals.CLOCKS",
-        .@"enum" = .{
-            .name = "AuxSrcPh",
+        .type_name = "AuxSrcPh",
+        .type = .{ .@"enum" = .{
             .bitsize = 4,
             .fields = .{
                 .{ .name = "clksrc_pll_sys", .value = 0 },
@@ -333,13 +520,13 @@
                 .{ .name = "clk_rtc", .value = 9 },
                 .{ .name = "clk_ref", .value = 10 },
             },
-        },
+        } },
         .apply_to = .{ "types.peripherals.CLOCKS.CLK_GPOUT2_CTRL.AUXSRC", "types.peripherals.CLOCKS.CLK_GPOUT3_CTRL.AUXSRC" },
     } },
-    .{ .add_enum_and_apply = .{
+    .{ .add_type_and_apply = .{
         .parent = "types.peripherals.CLOCKS",
-        .@"enum" = .{
-            .name = "AuxSrcExtra",
+        .type_name = "AuxSrcExtra",
+        .type = .{ .@"enum" = .{
             .bitsize = 3,
             .fields = .{
                 .{ .name = "clksrc_pll_usb", .value = 0 },
@@ -349,17 +536,17 @@
                 .{ .name = "clksrc_gpin0", .value = 4 },
                 .{ .name = "clksrc_gpin1", .value = 5 },
             },
-        },
+        } },
         .apply_to = .{
             "types.peripherals.CLOCKS.CLK_USB_CTRL.AUXSRC",
             "types.peripherals.CLOCKS.CLK_ADC_CTRL.AUXSRC",
             "types.peripherals.CLOCKS.CLK_RTC_CTRL.AUXSRC",
         },
     } },
-    .{ .add_enum_and_apply = .{
+    .{ .add_type_and_apply = .{
         .parent = "types.peripherals.BUSCTRL",
-        .@"enum" = .{
-            .name = "PerfSelect",
+        .type_name = "PerfSelect",
+        .type = .{ .@"enum" = .{
             .bitsize = 5,
             .fields = .{
                 .{ .name = "apb_contested", .value = 0 },
@@ -383,7 +570,7 @@
                 .{ .name = "rom_contested", .value = 18 },
                 .{ .name = "rom", .value = 19 },
             },
-        },
+        } },
         .apply_to = .{
             "types.peripherals.BUSCTRL.PERFSEL0.PERFSEL0",
             "types.peripherals.BUSCTRL.PERFSEL1.PERFSEL1",
@@ -391,10 +578,10 @@
             "types.peripherals.BUSCTRL.PERFSEL3.PERFSEL3",
         },
     } },
-    .{ .add_enum_and_apply = .{
+    .{ .add_type_and_apply = .{
         .parent = "types.peripherals.PADS_BANK0",
-        .@"enum" = .{
-            .name = "DriveStrength",
+        .type_name = "DriveStrength",
+        .type = .{ .@"enum" = .{
             .bitsize = 2,
             .fields = .{
                 .{ .name = "2mA", .value = 0 },
@@ -402,7 +589,7 @@
                 .{ .name = "8mA", .value = 2 },
                 .{ .name = "12mA", .value = 3 },
             },
-        },
+        } },
         .apply_to = .{
             "types.peripherals.PADS_BANK0.GPIO0.DRIVE",
             "types.peripherals.PADS_BANK0.GPIO1.DRIVE",
@@ -438,10 +625,10 @@
             "types.peripherals.PADS_BANK0.SWD.DRIVE",
         },
     } },
-    .{ .add_enum_and_apply = .{
+    .{ .add_type_and_apply = .{
         .parent = "types.peripherals.PADS_QSPI",
-        .@"enum" = .{
-            .name = "DriveStrength",
+        .type_name = "DriveStrength",
+        .type = .{ .@"enum" = .{
             .bitsize = 2,
             .fields = .{
                 .{ .name = "2mA", .value = 0 },
@@ -449,7 +636,7 @@
                 .{ .name = "8mA", .value = 2 },
                 .{ .name = "12mA", .value = 3 },
             },
-        },
+        } },
         .apply_to = .{
             "types.peripherals.PADS_QSPI.GPIO_QSPI_SCLK.DRIVE",
             "types.peripherals.PADS_QSPI.GPIO_QSPI_SD0.DRIVE",
diff --git a/port/raspberrypi/rp2xxx/patches/rp2350.zon b/port/raspberrypi/rp2xxx/patches/rp2350.zon
index 2f28af5b9..2696ae4c4 100644
--- a/port/raspberrypi/rp2xxx/patches/rp2350.zon
+++ b/port/raspberrypi/rp2xxx/patches/rp2350.zon
@@ -1,71 +1,354 @@
 .{
-    .{
-        .add_enum = .{
-            .parent = "types.peripherals.PADS_BANK0",
-            .@"enum" = .{
-                .name = "DriveStrength",
-                .bitsize = 2,
-                .fields = .{
-                    .{ .value = 0x0, .name = "2mA" },
-                    .{ .value = 0x1, .name = "4mA" },
-                    .{ .value = 0x2, .name = "8mA" },
-                    .{ .value = 0x3, .name = "12mA" },
+    .{ .add_type_and_apply = .{
+        .parent = "types.peripherals.IO_BANK0",
+        .type_name = "Override",
+        .type = .{ .@"enum" = .{
+            .bitsize = 2,
+            .fields = .{
+                .{ .value = 0, .name = "normal" },
+                .{ .value = 1, .name = "invert" },
+                .{ .value = 2, .name = "low" },
+                .{ .value = 3, .name = "high" },
+            },
+        } },
+        .apply_to = .{
+            "types.peripherals.IO_BANK0.GPIO0_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO0_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO0_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO0_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO1_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO1_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO1_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO1_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO2_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO2_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO2_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO2_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO3_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO3_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO3_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO3_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO4_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO4_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO4_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO4_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO5_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO5_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO5_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO5_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO6_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO6_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO6_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO6_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO7_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO7_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO7_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO7_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO8_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO8_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO8_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO8_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO9_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO9_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO9_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO9_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO10_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO10_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO10_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO10_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO11_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO11_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO11_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO11_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO12_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO12_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO12_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO12_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO13_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO13_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO13_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO13_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO14_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO14_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO14_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO14_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO15_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO15_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO15_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO15_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO16_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO16_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO16_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO16_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO17_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO17_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO17_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO17_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO18_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO18_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO18_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO18_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO19_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO19_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO19_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO19_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO20_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO20_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO20_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO20_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO21_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO21_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO21_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO21_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO22_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO22_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO22_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO22_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO23_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO23_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO23_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO23_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO24_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO24_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO24_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO24_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO25_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO25_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO25_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO25_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO26_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO26_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO26_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO26_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO27_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO27_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO27_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO27_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO28_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO28_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO28_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO28_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO29_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO29_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO29_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO29_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO30_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO30_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO30_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO30_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO31_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO31_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO31_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO31_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO32_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO32_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO32_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO32_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO33_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO33_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO33_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO33_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO34_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO34_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO34_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO34_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO35_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO35_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO35_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO35_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO36_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO36_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO36_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO36_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO37_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO37_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO37_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO37_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO38_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO38_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO38_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO38_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO39_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO39_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO39_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO39_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO40_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO40_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO40_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO40_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO41_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO41_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO41_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO41_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO42_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO42_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO42_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO42_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO43_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO43_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO43_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO43_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO44_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO44_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO44_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO44_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO45_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO45_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO45_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO45_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO46_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO46_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO46_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO46_CTRL.OUTOVER",
+            "types.peripherals.IO_BANK0.GPIO47_CTRL.INOVER",
+            "types.peripherals.IO_BANK0.GPIO47_CTRL.IRQOVER",
+            "types.peripherals.IO_BANK0.GPIO47_CTRL.OEOVER",
+            "types.peripherals.IO_BANK0.GPIO47_CTRL.OUTOVER",
+        },
+    } },
+    .{ .add_type_and_apply = .{
+        .parent = "types.peripherals.IO_BANK0",
+        .type_name = "Function",
+        .type = .{ .@"enum" = .{
+            .bitsize = 5,
+            .fields = .{
+                .{ .value = 0, .name = "hstx" },
+                .{ .value = 1, .name = "spi" },
+                .{ .value = 2, .name = "uart" },
+                .{ .value = 3, .name = "i2c" },
+                .{ .value = 4, .name = "pwm" },
+                .{ .value = 5, .name = "sio" },
+                .{ .value = 6, .name = "pio0" },
+                .{ .value = 7, .name = "pio1" },
+                .{ .value = 8, .name = "pio2" },
+                .{
+                    .value = 9,
+                    .name = "gpck",
+                    .description = "Also QMI_CS1 and Trace",
                 },
+                .{ .value = 10, .name = "usb" },
+                .{ .value = 11, .name = "uart_alt" },
+                .{ .value = 0x1f, .name = "disabled" },
             },
+        } },
+        .apply_to = .{
+            "types.peripherals.IO_BANK0.GPIO0_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO1_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO2_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO3_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO4_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO5_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO6_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO7_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO8_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO9_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO10_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO11_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO12_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO13_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO14_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO15_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO16_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO17_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO18_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO19_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO20_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO21_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO22_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO23_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO24_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO25_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO26_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO27_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO28_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO29_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO30_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO31_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO32_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO33_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO34_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO35_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO36_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO37_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO38_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO39_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO40_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO41_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO42_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO43_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO44_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO45_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO46_CTRL.FUNCSEL",
+            "types.peripherals.IO_BANK0.GPIO47_CTRL.FUNCSEL",
         },
-    },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO0.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO1.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO2.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO3.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO4.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO5.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO6.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO7.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO8.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO9.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO10.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO11.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO12.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO13.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO14.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO15.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO16.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO17.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO18.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO19.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO20.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO21.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO22.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO23.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO24.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO25.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO26.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO27.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO28.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO29.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO30.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO31.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO32.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO33.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO34.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO35.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO36.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO37.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO38.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO39.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO40.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO41.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO42.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO43.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO44.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO45.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO46.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.PADS_BANK0.GPIO47.DRIVE", .to = "types.peripherals.PADS_BANK0.DriveStrength" } },
-    .{ .add_enum = .{
+    } },
+    .{ .add_type_and_apply = .{
+        .parent = "types.peripherals.PADS_BANK0",
+        .type_name = "DriveStrength",
+        .type = .{ .@"enum" = .{
+            .bitsize = 2,
+            .fields = .{
+                .{ .value = 0x0, .name = "2mA" },
+                .{ .value = 0x1, .name = "4mA" },
+                .{ .value = 0x2, .name = "8mA" },
+                .{ .value = 0x3, .name = "12mA" },
+            },
+        } },
+        .apply_to = .{
+            "types.peripherals.PADS_BANK0.GPIO0.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO1.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO2.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO3.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO4.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO5.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO6.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO7.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO8.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO9.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO10.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO11.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO12.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO13.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO14.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO15.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO16.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO17.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO18.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO19.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO20.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO21.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO22.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO23.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO24.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO25.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO26.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO27.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO28.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO29.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO30.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO31.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO32.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO33.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO34.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO35.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO36.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO37.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO38.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO39.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO40.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO41.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO42.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO43.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO44.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO45.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO46.DRIVE",
+            "types.peripherals.PADS_BANK0.GPIO47.DRIVE",
+        },
+    } },
+    .{ .add_type_and_apply = .{
         .parent = "types.peripherals.USB_DPRAM",
-        .@"enum" = .{
-            .name = "EndpointType",
+        .type_name = "EndpointType",
+        .type = .{ .@"enum" = .{
             .bitsize = 2,
             .fields = .{
                 .{ .value = 0x0, .name = "control" },
@@ -73,155 +356,157 @@
                 .{ .value = 0x2, .name = "bulk" },
                 .{ .value = 0x3, .name = "interrupt" },
             },
+        } },
+        .apply_to = .{
+            "types.peripherals.USB_DPRAM.EP1_IN_CONTROL.ENDPOINT_TYPE",
+            "types.peripherals.USB_DPRAM.EP1_OUT_CONTROL.ENDPOINT_TYPE",
+            "types.peripherals.USB_DPRAM.EP2_IN_CONTROL.ENDPOINT_TYPE",
+            "types.peripherals.USB_DPRAM.EP2_OUT_CONTROL.ENDPOINT_TYPE",
+            "types.peripherals.USB_DPRAM.EP3_IN_CONTROL.ENDPOINT_TYPE",
+            "types.peripherals.USB_DPRAM.EP3_OUT_CONTROL.ENDPOINT_TYPE",
+            "types.peripherals.USB_DPRAM.EP4_IN_CONTROL.ENDPOINT_TYPE",
+            "types.peripherals.USB_DPRAM.EP4_OUT_CONTROL.ENDPOINT_TYPE",
+            "types.peripherals.USB_DPRAM.EP5_IN_CONTROL.ENDPOINT_TYPE",
+            "types.peripherals.USB_DPRAM.EP5_OUT_CONTROL.ENDPOINT_TYPE",
+            "types.peripherals.USB_DPRAM.EP6_IN_CONTROL.ENDPOINT_TYPE",
+            "types.peripherals.USB_DPRAM.EP6_OUT_CONTROL.ENDPOINT_TYPE",
+            "types.peripherals.USB_DPRAM.EP7_IN_CONTROL.ENDPOINT_TYPE",
+            "types.peripherals.USB_DPRAM.EP7_OUT_CONTROL.ENDPOINT_TYPE",
+            "types.peripherals.USB_DPRAM.EP8_IN_CONTROL.ENDPOINT_TYPE",
+            "types.peripherals.USB_DPRAM.EP8_OUT_CONTROL.ENDPOINT_TYPE",
+            "types.peripherals.USB_DPRAM.EP9_IN_CONTROL.ENDPOINT_TYPE",
+            "types.peripherals.USB_DPRAM.EP9_OUT_CONTROL.ENDPOINT_TYPE",
+            "types.peripherals.USB_DPRAM.EP10_IN_CONTROL.ENDPOINT_TYPE",
+            "types.peripherals.USB_DPRAM.EP10_OUT_CONTROL.ENDPOINT_TYPE",
+            "types.peripherals.USB_DPRAM.EP11_IN_CONTROL.ENDPOINT_TYPE",
+            "types.peripherals.USB_DPRAM.EP11_OUT_CONTROL.ENDPOINT_TYPE",
+            "types.peripherals.USB_DPRAM.EP12_IN_CONTROL.ENDPOINT_TYPE",
+            "types.peripherals.USB_DPRAM.EP12_OUT_CONTROL.ENDPOINT_TYPE",
+            "types.peripherals.USB_DPRAM.EP13_IN_CONTROL.ENDPOINT_TYPE",
+            "types.peripherals.USB_DPRAM.EP13_OUT_CONTROL.ENDPOINT_TYPE",
+            "types.peripherals.USB_DPRAM.EP14_IN_CONTROL.ENDPOINT_TYPE",
+            "types.peripherals.USB_DPRAM.EP14_OUT_CONTROL.ENDPOINT_TYPE",
+            "types.peripherals.USB_DPRAM.EP15_IN_CONTROL.ENDPOINT_TYPE",
+            "types.peripherals.USB_DPRAM.EP15_OUT_CONTROL.ENDPOINT_TYPE",
         },
     } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.USB_DPRAM.EP1_IN_CONTROL.ENDPOINT_TYPE", .to = "types.peripherals.USB_DPRAM.EndpointType" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.USB_DPRAM.EP1_OUT_CONTROL.ENDPOINT_TYPE", .to = "types.peripherals.USB_DPRAM.EndpointType" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.USB_DPRAM.EP2_IN_CONTROL.ENDPOINT_TYPE", .to = "types.peripherals.USB_DPRAM.EndpointType" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.USB_DPRAM.EP2_OUT_CONTROL.ENDPOINT_TYPE", .to = "types.peripherals.USB_DPRAM.EndpointType" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.USB_DPRAM.EP3_IN_CONTROL.ENDPOINT_TYPE", .to = "types.peripherals.USB_DPRAM.EndpointType" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.USB_DPRAM.EP3_OUT_CONTROL.ENDPOINT_TYPE", .to = "types.peripherals.USB_DPRAM.EndpointType" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.USB_DPRAM.EP4_IN_CONTROL.ENDPOINT_TYPE", .to = "types.peripherals.USB_DPRAM.EndpointType" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.USB_DPRAM.EP4_OUT_CONTROL.ENDPOINT_TYPE", .to = "types.peripherals.USB_DPRAM.EndpointType" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.USB_DPRAM.EP5_IN_CONTROL.ENDPOINT_TYPE", .to = "types.peripherals.USB_DPRAM.EndpointType" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.USB_DPRAM.EP5_OUT_CONTROL.ENDPOINT_TYPE", .to = "types.peripherals.USB_DPRAM.EndpointType" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.USB_DPRAM.EP6_IN_CONTROL.ENDPOINT_TYPE", .to = "types.peripherals.USB_DPRAM.EndpointType" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.USB_DPRAM.EP6_OUT_CONTROL.ENDPOINT_TYPE", .to = "types.peripherals.USB_DPRAM.EndpointType" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.USB_DPRAM.EP7_IN_CONTROL.ENDPOINT_TYPE", .to = "types.peripherals.USB_DPRAM.EndpointType" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.USB_DPRAM.EP7_OUT_CONTROL.ENDPOINT_TYPE", .to = "types.peripherals.USB_DPRAM.EndpointType" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.USB_DPRAM.EP8_IN_CONTROL.ENDPOINT_TYPE", .to = "types.peripherals.USB_DPRAM.EndpointType" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.USB_DPRAM.EP8_OUT_CONTROL.ENDPOINT_TYPE", .to = "types.peripherals.USB_DPRAM.EndpointType" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.USB_DPRAM.EP9_IN_CONTROL.ENDPOINT_TYPE", .to = "types.peripherals.USB_DPRAM.EndpointType" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.USB_DPRAM.EP9_OUT_CONTROL.ENDPOINT_TYPE", .to = "types.peripherals.USB_DPRAM.EndpointType" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.USB_DPRAM.EP10_IN_CONTROL.ENDPOINT_TYPE", .to = "types.peripherals.USB_DPRAM.EndpointType" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.USB_DPRAM.EP10_OUT_CONTROL.ENDPOINT_TYPE", .to = "types.peripherals.USB_DPRAM.EndpointType" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.USB_DPRAM.EP11_IN_CONTROL.ENDPOINT_TYPE", .to = "types.peripherals.USB_DPRAM.EndpointType" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.USB_DPRAM.EP11_OUT_CONTROL.ENDPOINT_TYPE", .to = "types.peripherals.USB_DPRAM.EndpointType" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.USB_DPRAM.EP12_IN_CONTROL.ENDPOINT_TYPE", .to = "types.peripherals.USB_DPRAM.EndpointType" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.USB_DPRAM.EP12_OUT_CONTROL.ENDPOINT_TYPE", .to = "types.peripherals.USB_DPRAM.EndpointType" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.USB_DPRAM.EP13_IN_CONTROL.ENDPOINT_TYPE", .to = "types.peripherals.USB_DPRAM.EndpointType" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.USB_DPRAM.EP13_OUT_CONTROL.ENDPOINT_TYPE", .to = "types.peripherals.USB_DPRAM.EndpointType" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.USB_DPRAM.EP14_IN_CONTROL.ENDPOINT_TYPE", .to = "types.peripherals.USB_DPRAM.EndpointType" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.USB_DPRAM.EP14_OUT_CONTROL.ENDPOINT_TYPE", .to = "types.peripherals.USB_DPRAM.EndpointType" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.USB_DPRAM.EP15_IN_CONTROL.ENDPOINT_TYPE", .to = "types.peripherals.USB_DPRAM.EndpointType" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.USB_DPRAM.EP15_OUT_CONTROL.ENDPOINT_TYPE", .to = "types.peripherals.USB_DPRAM.EndpointType" } },
-    .{
-        .add_enum = .{
-            .parent = "types.peripherals.DMA",
-            .@"enum" = .{
-                .name = "DataSize",
-                .bitsize = 2,
-                .fields = .{
-                    .{ .value = 0x0, .name = "size_8" },
-                    .{ .value = 0x1, .name = "size_16" },
-                    .{ .value = 0x2, .name = "size_32" },
-                },
+    .{ .add_type_and_apply = .{
+        .parent = "types.peripherals.DMA",
+        .type_name = "DataSize",
+        .type = .{ .@"enum" = .{
+            .bitsize = 2,
+            .fields = .{
+                .{ .value = 0x0, .name = "size_8" },
+                .{ .value = 0x1, .name = "size_16" },
+                .{ .value = 0x2, .name = "size_32" },
             },
+        } },
+        .apply_to = .{
+            "types.peripherals.DMA.CH0_CTRL_TRIG.DATA_SIZE",
+            "types.peripherals.DMA.CH1_CTRL_TRIG.DATA_SIZE",
+            "types.peripherals.DMA.CH2_CTRL_TRIG.DATA_SIZE",
+            "types.peripherals.DMA.CH3_CTRL_TRIG.DATA_SIZE",
+            "types.peripherals.DMA.CH4_CTRL_TRIG.DATA_SIZE",
+            "types.peripherals.DMA.CH5_CTRL_TRIG.DATA_SIZE",
+            "types.peripherals.DMA.CH6_CTRL_TRIG.DATA_SIZE",
+            "types.peripherals.DMA.CH7_CTRL_TRIG.DATA_SIZE",
+            "types.peripherals.DMA.CH8_CTRL_TRIG.DATA_SIZE",
+            "types.peripherals.DMA.CH9_CTRL_TRIG.DATA_SIZE",
+            "types.peripherals.DMA.CH10_CTRL_TRIG.DATA_SIZE",
+            "types.peripherals.DMA.CH11_CTRL_TRIG.DATA_SIZE",
+            "types.peripherals.DMA.CH12_CTRL_TRIG.DATA_SIZE",
+            "types.peripherals.DMA.CH13_CTRL_TRIG.DATA_SIZE",
+            "types.peripherals.DMA.CH14_CTRL_TRIG.DATA_SIZE",
+            "types.peripherals.DMA.CH15_CTRL_TRIG.DATA_SIZE",
         },
-    },
-    .{ .set_enum_type = .{ .of = "types.peripherals.DMA.CH0_CTRL_TRIG.DATA_SIZE", .to = "types.peripherals.DMA.DataSize" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.DMA.CH1_CTRL_TRIG.DATA_SIZE", .to = "types.peripherals.DMA.DataSize" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.DMA.CH2_CTRL_TRIG.DATA_SIZE", .to = "types.peripherals.DMA.DataSize" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.DMA.CH3_CTRL_TRIG.DATA_SIZE", .to = "types.peripherals.DMA.DataSize" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.DMA.CH4_CTRL_TRIG.DATA_SIZE", .to = "types.peripherals.DMA.DataSize" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.DMA.CH5_CTRL_TRIG.DATA_SIZE", .to = "types.peripherals.DMA.DataSize" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.DMA.CH6_CTRL_TRIG.DATA_SIZE", .to = "types.peripherals.DMA.DataSize" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.DMA.CH7_CTRL_TRIG.DATA_SIZE", .to = "types.peripherals.DMA.DataSize" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.DMA.CH8_CTRL_TRIG.DATA_SIZE", .to = "types.peripherals.DMA.DataSize" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.DMA.CH9_CTRL_TRIG.DATA_SIZE", .to = "types.peripherals.DMA.DataSize" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.DMA.CH10_CTRL_TRIG.DATA_SIZE", .to = "types.peripherals.DMA.DataSize" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.DMA.CH11_CTRL_TRIG.DATA_SIZE", .to = "types.peripherals.DMA.DataSize" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.DMA.CH12_CTRL_TRIG.DATA_SIZE", .to = "types.peripherals.DMA.DataSize" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.DMA.CH13_CTRL_TRIG.DATA_SIZE", .to = "types.peripherals.DMA.DataSize" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.DMA.CH14_CTRL_TRIG.DATA_SIZE", .to = "types.peripherals.DMA.DataSize" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.DMA.CH15_CTRL_TRIG.DATA_SIZE", .to = "types.peripherals.DMA.DataSize" } },
-    .{
-        .add_enum = .{
-            .parent = "types.peripherals.DMA",
-            .@"enum" = .{
-                .name = "Dreq",
-                .bitsize = 6,
-                .fields = .{
-                    .{ .value = 0, .name = "pio0_tx0" },
-                    .{ .value = 1, .name = "pio0_tx1" },
-                    .{ .value = 2, .name = "pio0_tx2" },
-                    .{ .value = 3, .name = "pio0_tx3" },
-                    .{ .value = 4, .name = "pio0_rx0" },
-                    .{ .value = 5, .name = "pio0_rx1" },
-                    .{ .value = 6, .name = "pio0_rx2" },
-                    .{ .value = 7, .name = "pio0_rx3" },
-                    .{ .value = 8, .name = "pio1_tx0" },
-                    .{ .value = 9, .name = "pio1_tx1" },
-                    .{ .value = 10, .name = "pio1_tx2" },
-                    .{ .value = 11, .name = "pio1_tx3" },
-                    .{ .value = 12, .name = "pio1_rx0" },
-                    .{ .value = 13, .name = "pio1_rx1" },
-                    .{ .value = 14, .name = "pio1_rx2" },
-                    .{ .value = 15, .name = "pio1_rx3" },
-                    .{ .value = 16, .name = "pio2_tx0" },
-                    .{ .value = 17, .name = "pio2_tx1" },
-                    .{ .value = 18, .name = "pio2_tx2" },
-                    .{ .value = 19, .name = "pio2_tx3" },
-                    .{ .value = 20, .name = "pio2_rx0" },
-                    .{ .value = 21, .name = "pio2_rx1" },
-                    .{ .value = 22, .name = "pio2_rx2" },
-                    .{ .value = 23, .name = "pio2_rx3" },
-                    .{ .value = 24, .name = "spi0_tx" },
-                    .{ .value = 25, .name = "spi0_rx" },
-                    .{ .value = 26, .name = "spi1_tx" },
-                    .{ .value = 27, .name = "spi1_rx" },
-                    .{ .value = 28, .name = "uart0_tx" },
-                    .{ .value = 29, .name = "uart0_rx" },
-                    .{ .value = 30, .name = "uart1_tx" },
-                    .{ .value = 31, .name = "uart1_rx" },
-                    .{ .value = 32, .name = "pwm_wrap0" },
-                    .{ .value = 33, .name = "pwm_wrap1" },
-                    .{ .value = 34, .name = "pwm_wrap2" },
-                    .{ .value = 35, .name = "pwm_wrap3" },
-                    .{ .value = 36, .name = "pwm_wrap4" },
-                    .{ .value = 37, .name = "pwm_wrap5" },
-                    .{ .value = 38, .name = "pwm_wrap6" },
-                    .{ .value = 39, .name = "pwm_wrap7" },
-                    .{ .value = 40, .name = "pwm_wrap8" },
-                    .{ .value = 41, .name = "pwm_wrap9" },
-                    .{ .value = 42, .name = "pwm_wrap10" },
-                    .{ .value = 43, .name = "pwm_wrap11" },
-                    .{ .value = 44, .name = "i2c0_tx" },
-                    .{ .value = 45, .name = "i2c0_rx" },
-                    .{ .value = 46, .name = "i2c1_tx" },
-                    .{ .value = 47, .name = "i2c1_rx" },
-                    .{ .value = 48, .name = "adc" },
-                    .{ .value = 49, .name = "xip_stream" },
-                    .{ .value = 50, .name = "xip_qmitx" },
-                    .{ .value = 51, .name = "xip_qmirx" },
-                    .{ .value = 52, .name = "hstx" },
-                    .{ .value = 53, .name = "coresight" },
-                    .{ .value = 54, .name = "sha256" },
-                    .{ .value = 59, .name = "timer0" },
-                    .{ .value = 60, .name = "timer1" },
-                    .{ .value = 61, .name = "timer2" },
-                    .{ .value = 62, .name = "timer3" },
-                    .{ .value = 63, .name = "permanent" },
-                },
+    } },
+    .{ .add_type_and_apply = .{
+        .parent = "types.peripherals.DMA",
+        .type_name = "Dreq",
+        .type = .{ .@"enum" = .{
+            .bitsize = 6,
+            .fields = .{
+                .{ .value = 0, .name = "pio0_tx0" },
+                .{ .value = 1, .name = "pio0_tx1" },
+                .{ .value = 2, .name = "pio0_tx2" },
+                .{ .value = 3, .name = "pio0_tx3" },
+                .{ .value = 4, .name = "pio0_rx0" },
+                .{ .value = 5, .name = "pio0_rx1" },
+                .{ .value = 6, .name = "pio0_rx2" },
+                .{ .value = 7, .name = "pio0_rx3" },
+                .{ .value = 8, .name = "pio1_tx0" },
+                .{ .value = 9, .name = "pio1_tx1" },
+                .{ .value = 10, .name = "pio1_tx2" },
+                .{ .value = 11, .name = "pio1_tx3" },
+                .{ .value = 12, .name = "pio1_rx0" },
+                .{ .value = 13, .name = "pio1_rx1" },
+                .{ .value = 14, .name = "pio1_rx2" },
+                .{ .value = 15, .name = "pio1_rx3" },
+                .{ .value = 16, .name = "pio2_tx0" },
+                .{ .value = 17, .name = "pio2_tx1" },
+                .{ .value = 18, .name = "pio2_tx2" },
+                .{ .value = 19, .name = "pio2_tx3" },
+                .{ .value = 20, .name = "pio2_rx0" },
+                .{ .value = 21, .name = "pio2_rx1" },
+                .{ .value = 22, .name = "pio2_rx2" },
+                .{ .value = 23, .name = "pio2_rx3" },
+                .{ .value = 24, .name = "spi0_tx" },
+                .{ .value = 25, .name = "spi0_rx" },
+                .{ .value = 26, .name = "spi1_tx" },
+                .{ .value = 27, .name = "spi1_rx" },
+                .{ .value = 28, .name = "uart0_tx" },
+                .{ .value = 29, .name = "uart0_rx" },
+                .{ .value = 30, .name = "uart1_tx" },
+                .{ .value = 31, .name = "uart1_rx" },
+                .{ .value = 32, .name = "pwm_wrap0" },
+                .{ .value = 33, .name = "pwm_wrap1" },
+                .{ .value = 34, .name = "pwm_wrap2" },
+                .{ .value = 35, .name = "pwm_wrap3" },
+                .{ .value = 36, .name = "pwm_wrap4" },
+                .{ .value = 37, .name = "pwm_wrap5" },
+                .{ .value = 38, .name = "pwm_wrap6" },
+                .{ .value = 39, .name = "pwm_wrap7" },
+                .{ .value = 40, .name = "pwm_wrap8" },
+                .{ .value = 41, .name = "pwm_wrap9" },
+                .{ .value = 42, .name = "pwm_wrap10" },
+                .{ .value = 43, .name = "pwm_wrap11" },
+                .{ .value = 44, .name = "i2c0_tx" },
+                .{ .value = 45, .name = "i2c0_rx" },
+                .{ .value = 46, .name = "i2c1_tx" },
+                .{ .value = 47, .name = "i2c1_rx" },
+                .{ .value = 48, .name = "adc" },
+                .{ .value = 49, .name = "xip_stream" },
+                .{ .value = 50, .name = "xip_qmitx" },
+                .{ .value = 51, .name = "xip_qmirx" },
+                .{ .value = 52, .name = "hstx" },
+                .{ .value = 53, .name = "coresight" },
+                .{ .value = 54, .name = "sha256" },
+                .{ .value = 59, .name = "timer0" },
+                .{ .value = 60, .name = "timer1" },
+                .{ .value = 61, .name = "timer2" },
+                .{ .value = 62, .name = "timer3" },
+                .{ .value = 63, .name = "permanent" },
             },
+        } },
+        .apply_to = .{
+            "types.peripherals.DMA.CH0_CTRL_TRIG.TREQ_SEL",
+            "types.peripherals.DMA.CH1_CTRL_TRIG.TREQ_SEL",
+            "types.peripherals.DMA.CH2_CTRL_TRIG.TREQ_SEL",
+            "types.peripherals.DMA.CH3_CTRL_TRIG.TREQ_SEL",
+            "types.peripherals.DMA.CH4_CTRL_TRIG.TREQ_SEL",
+            "types.peripherals.DMA.CH5_CTRL_TRIG.TREQ_SEL",
+            "types.peripherals.DMA.CH6_CTRL_TRIG.TREQ_SEL",
+            "types.peripherals.DMA.CH7_CTRL_TRIG.TREQ_SEL",
+            "types.peripherals.DMA.CH8_CTRL_TRIG.TREQ_SEL",
+            "types.peripherals.DMA.CH9_CTRL_TRIG.TREQ_SEL",
+            "types.peripherals.DMA.CH10_CTRL_TRIG.TREQ_SEL",
+            "types.peripherals.DMA.CH11_CTRL_TRIG.TREQ_SEL",
+            "types.peripherals.DMA.CH12_CTRL_TRIG.TREQ_SEL",
+            "types.peripherals.DMA.CH13_CTRL_TRIG.TREQ_SEL",
+            "types.peripherals.DMA.CH14_CTRL_TRIG.TREQ_SEL",
+            "types.peripherals.DMA.CH15_CTRL_TRIG.TREQ_SEL",
         },
-    },
-    .{ .set_enum_type = .{ .of = "types.peripherals.DMA.CH0_CTRL_TRIG.TREQ_SEL", .to = "types.peripherals.DMA.Dreq" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.DMA.CH1_CTRL_TRIG.TREQ_SEL", .to = "types.peripherals.DMA.Dreq" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.DMA.CH2_CTRL_TRIG.TREQ_SEL", .to = "types.peripherals.DMA.Dreq" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.DMA.CH3_CTRL_TRIG.TREQ_SEL", .to = "types.peripherals.DMA.Dreq" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.DMA.CH4_CTRL_TRIG.TREQ_SEL", .to = "types.peripherals.DMA.Dreq" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.DMA.CH5_CTRL_TRIG.TREQ_SEL", .to = "types.peripherals.DMA.Dreq" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.DMA.CH6_CTRL_TRIG.TREQ_SEL", .to = "types.peripherals.DMA.Dreq" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.DMA.CH7_CTRL_TRIG.TREQ_SEL", .to = "types.peripherals.DMA.Dreq" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.DMA.CH8_CTRL_TRIG.TREQ_SEL", .to = "types.peripherals.DMA.Dreq" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.DMA.CH9_CTRL_TRIG.TREQ_SEL", .to = "types.peripherals.DMA.Dreq" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.DMA.CH10_CTRL_TRIG.TREQ_SEL", .to = "types.peripherals.DMA.Dreq" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.DMA.CH11_CTRL_TRIG.TREQ_SEL", .to = "types.peripherals.DMA.Dreq" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.DMA.CH12_CTRL_TRIG.TREQ_SEL", .to = "types.peripherals.DMA.Dreq" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.DMA.CH13_CTRL_TRIG.TREQ_SEL", .to = "types.peripherals.DMA.Dreq" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.DMA.CH14_CTRL_TRIG.TREQ_SEL", .to = "types.peripherals.DMA.Dreq" } },
-    .{ .set_enum_type = .{ .of = "types.peripherals.DMA.CH15_CTRL_TRIG.TREQ_SEL", .to = "types.peripherals.DMA.Dreq" } },
+    } },
     .{ .add_interrupt = .{
         .device_name = "RP2350",
         .idx = 40,
diff --git a/port/raspberrypi/rp2xxx/src/hal/gpio.zig b/port/raspberrypi/rp2xxx/src/hal/gpio.zig
index 4cb8a9102..44568ee53 100644
--- a/port/raspberrypi/rp2xxx/src/hal/gpio.zig
+++ b/port/raspberrypi/rp2xxx/src/hal/gpio.zig
@@ -1,5 +1,3 @@
-const std = @import("std");
-
 const microzig = @import("microzig");
 const peripherals = microzig.chip.peripherals;
 const SIO = peripherals.SIO;
@@ -9,61 +7,23 @@ const hw = @import("hw.zig");
 
 const chip = @import("compatibility.zig").chip;
 
-const resets = @import("resets.zig");
 const NUM_BANK0_GPIOS = switch (chip) {
     .RP2040 => 30,
     .RP2350 => 48,
 };
 
-pub const Function =
-    switch (chip) {
-        .RP2040 => enum(u5) {
-            xip = 0,
-            spi,
-            uart,
-            i2c,
-            pwm,
-            sio,
-            pio0,
-            pio1,
-            gpck,
-            usb,
-            disabled = 0x1f,
-        },
-        .RP2350 => enum(u5) {
-            hstx = 0,
-            spi,
-            uart,
-            i2c,
-            pwm,
-            sio,
-            pio0,
-            pio1,
-            pio2,
-            gpck, // Also QMI_CS1 and Trace
-            usb,
-            uart_alt,
-            disabled = 0x1f,
-        },
-    };
-
 pub const Direction = enum(u1) {
     in,
     out,
 };
 
-pub const Override = enum(u2) {
-    normal,
-    invert,
-    low,
-    high,
-};
-
 pub const SlewRate = enum(u1) {
     slow,
     fast,
 };
 
+pub const Function = microzig.chip.types.peripherals.IO_BANK0.Function;
+pub const Override = microzig.chip.types.peripherals.IO_BANK0.Override;
 pub const DriveStrength = microzig.chip.types.peripherals.PADS_BANK0.DriveStrength;
 
 pub const Pull = enum {
@@ -259,37 +219,10 @@ pub const Mask =
 pub const Pin = enum(u6) {
     _,
 
-    pub const Regs =
-        switch (chip) {
-            .RP2040 => extern struct {
-                status: @TypeOf(IO_BANK0.GPIO0_STATUS),
-                ctrl: microzig.mmio.Mmio(packed struct(u32) {
-                    FUNCSEL: Function,
-                    reserved8: u3 = 0,
-                    OUTOVER: Override,
-                    reserved12: u2 = 0,
-                    OEOVER: Override,
-                    reserved16: u2 = 0,
-                    INOVER: Override,
-                    reserved28: u10 = 0,
-                    IRQOVER: Override,
-                    padding: u2 = 0,
-                }),
-            },
-            .RP2350 => extern struct {
-                status: @TypeOf(IO_BANK0.GPIO0_STATUS),
-                ctrl: microzig.mmio.Mmio(packed struct(u32) {
-                    FUNCSEL: Function,
-                    reserved12: u7 = 0,
-                    OUTOVER: Override,
-                    OEOVER: Override,
-                    INOVER: Override,
-                    reserved28: u10 = 0,
-                    IRQOVER: Override,
-                    padding: u2 = 0,
-                }),
-            },
-        };
+    pub const Regs = struct {
+        status: @TypeOf(IO_BANK0.GPIO0_STATUS),
+        ctrl: @TypeOf(IO_BANK0.GPIO0_CTRL),
+    };
 
     pub const RegsArray = switch (chip) {
         .RP2040 => *volatile [30]Regs,
diff --git a/port/raspberrypi/rp2xxx/src/hal/i2c_slave.zig b/port/raspberrypi/rp2xxx/src/hal/i2c_slave.zig
index a3fdd9145..78708d8c1 100644
--- a/port/raspberrypi/rp2xxx/src/hal/i2c_slave.zig
+++ b/port/raspberrypi/rp2xxx/src/hal/i2c_slave.zig
@@ -44,20 +44,14 @@
 //! parameter set to `false`.  The user can return 0 if no more data is available.
 //!
 
-const std = @import("std");
 const microzig = @import("microzig");
 const i2c = microzig.hal.i2c;
 
-const mdf = microzig.drivers;
 const peripherals = microzig.chip.peripherals;
 const I2C0 = peripherals.I2C0;
 const I2C1 = peripherals.I2C1;
 const I2cRegs = microzig.chip.types.peripherals.I2C0;
 
-const fifo_length = 16;
-
-const gpio = @import("gpio.zig");
-
 pub const RXCallback = *const fn (data: []const u8, first: bool, last: bool, gen_call: bool, param: ?*anyopaque) void;
 pub const TXCallback = *const fn (data: []u8, first: bool, param: ?*anyopaque) usize;
 
@@ -295,13 +289,13 @@ fn isr_common(self: *Self) void {
             // If we have no more data, fill the TX FIFO with zeros
 
             while (self.regs.IC_STATUS.read().TFNF == .NOT_FULL) {
-                self.regs.IC_DATA_CMD.write_raw(0);
+                self.regs.IC_DATA_CMD.raw = 0;
             }
         } else {
             // Fill the TX FIFO with data from the transfer buffer
 
             while (self.transfer_index < self.transfer_length and self.regs.IC_STATUS.read().TFNF == .NOT_FULL) {
-                self.regs.IC_DATA_CMD.write_raw(@intCast(self.transfer_buffer[self.transfer_index]));
+                self.regs.IC_DATA_CMD.raw = @intCast(self.transfer_buffer[self.transfer_index]);
                 self.transfer_index += 1;
             }
         }
diff --git a/port/raspberrypi/rp2xxx/src/hal/pio/common.zig b/port/raspberrypi/rp2xxx/src/hal/pio/common.zig
index 8a2a58d9a..429c8c7c1 100644
--- a/port/raspberrypi/rp2xxx/src/hal/pio/common.zig
+++ b/port/raspberrypi/rp2xxx/src/hal/pio/common.zig
@@ -12,7 +12,6 @@ pub const PIO1 = microzig.chip.peripherals.PIO1;
 pub const assembler = @import("assembler.zig");
 const encoder = @import("assembler/encoder.zig");
 const gpio = @import("../gpio.zig");
-const hw = @import("../hw.zig");
 
 pub const Instruction = encoder.Instruction;
 pub const Program = assembler.Program;
@@ -217,7 +216,7 @@ pub fn PioImpl(EnumType: type, chip: Chip) type {
             const mask = @as(u32, 1) << index;
             var val = self.get_regs().INPUT_SYNC_BYPASS.raw;
             val |= mask;
-            self.get_regs().INPUT_SYNC_BYPASS.write_raw(val);
+            self.get_regs().INPUT_SYNC_BYPASS.raw = val;
         }
 
         pub fn get_sm_regs(self: EnumType, sm: StateMachine) *volatile StateMachine.Regs {
diff --git a/port/raspberrypi/rp2xxx/src/hal/resets.zig b/port/raspberrypi/rp2xxx/src/hal/resets.zig
index 6aafe637f..bbfb4752b 100644
--- a/port/raspberrypi/rp2xxx/src/hal/resets.zig
+++ b/port/raspberrypi/rp2xxx/src/hal/resets.zig
@@ -1,5 +1,4 @@
 const std = @import("std");
-const EnumField = std.builtin.Type.EnumField;
 
 const microzig = @import("microzig");
 const RESETS = microzig.chip.peripherals.RESETS;
@@ -85,24 +84,24 @@ pub const Mask =
 pub fn reset(mask: Mask) void {
     const raw_mask: u32 = @bitCast(mask);
 
-    RESETS.RESET.write_raw(raw_mask);
-    RESETS.RESET.write_raw(0);
+    RESETS.RESET.raw = raw_mask;
+    RESETS.RESET.raw = 0;
 
     wait_for_reset_done(mask);
 }
 
 pub inline fn reset_block(mask: Mask) void {
-    hw.set_alias(RESETS).RESET.write_raw(@bitCast(mask));
+    hw.set_alias(RESETS).RESET.raw = @bitCast(mask);
 }
 
 pub inline fn unreset_block(mask: Mask) void {
-    hw.clear_alias(RESETS).RESET.write_raw(@bitCast(mask));
+    hw.clear_alias(RESETS).RESET.raw = @bitCast(mask);
 }
 
 pub fn unreset_block_wait(mask: Mask) void {
     const raw_mask: u32 = @bitCast(mask);
 
-    hw.clear_alias(RESETS).RESET.write_raw(raw_mask);
+    hw.clear_alias(RESETS).RESET.raw = raw_mask;
 
     wait_for_reset_done(mask);
 }
diff --git a/port/raspberrypi/rp2xxx/src/hal/spi.zig b/port/raspberrypi/rp2xxx/src/hal/spi.zig
index 7c0c7ea5f..0c0090b0c 100644
--- a/port/raspberrypi/rp2xxx/src/hal/spi.zig
+++ b/port/raspberrypi/rp2xxx/src/hal/spi.zig
@@ -6,8 +6,6 @@ const SPI1_reg = peripherals.SPI1;
 
 const clocks = @import("clocks.zig");
 const dma = @import("dma.zig");
-const resets = @import("resets.zig");
-const time = @import("time.zig");
 const hw = @import("hw.zig");
 
 const SpiRegs = microzig.chip.types.peripherals.SPI0;
@@ -213,7 +211,7 @@ pub const SPI = enum(u1) {
         var count: usize = 0;
         while (spi.is_writable()) {
             const element = src_iter.next_element() orelse break;
-            spi_regs.SSPDR.write_raw(element.value);
+            spi_regs.SSPDR.raw = element.value;
             count += 1;
         }
         spi_regs.SSPCR1.modify(.{
@@ -230,7 +228,7 @@ pub const SPI = enum(u1) {
         });
         var tx_remaining = repeat_count;
         while (tx_remaining > 0 and spi.is_writable()) {
-            spi_regs.SSPDR.write_raw(repeated_byte);
+            spi_regs.SSPDR.raw = repeated_byte;
             tx_remaining -= 1;
         }
         spi_regs.SSPCR1.modify(.{
@@ -279,7 +277,7 @@ pub const SPI = enum(u1) {
         while (rx_remaining > 0 or tx_remaining > 0) {
             if (tx_remaining > 0 and spi.is_writable() and rx_remaining < tx_remaining + fifo_depth) {
                 const element = src_iter.next_element() orelse unreachable;
-                spi_regs.SSPDR.write_raw(element.value);
+                spi_regs.SSPDR.raw = element.value;
                 tx_remaining -= 1;
             }
             if (rx_remaining > 0 and spi.is_readable()) {
@@ -330,7 +328,7 @@ pub const SPI = enum(u1) {
             while (!spi.is_writable()) {
                 hw.tight_loop_contents();
             }
-            spi_regs.SSPDR.write_raw(element.value);
+            spi_regs.SSPDR.raw = element.value;
         }
 
         // Drain RX FIFO, then wait for shifting to finish (which may be *after*
@@ -387,7 +385,7 @@ pub const SPI = enum(u1) {
         tx_remaining -= spi.prime_tx_fifo_repeated(PacketType, repeated_tx_data, tx_remaining);
         while (rx_remaining > 0 or tx_remaining > 0) {
             if (tx_remaining > 0 and spi.is_writable() and rx_remaining < tx_remaining + fifo_depth) {
-                spi_regs.SSPDR.write_raw(repeated_tx_data);
+                spi_regs.SSPDR.raw = repeated_tx_data;
                 tx_remaining -= 1;
             }
             if (rx_remaining > 0 and spi.is_readable()) {
diff --git a/port/raspberrypi/rp2xxx/src/hal/system_timer.zig b/port/raspberrypi/rp2xxx/src/hal/system_timer.zig
index 9b9a2a955..c58ba8055 100644
--- a/port/raspberrypi/rp2xxx/src/hal/system_timer.zig
+++ b/port/raspberrypi/rp2xxx/src/hal/system_timer.zig
@@ -43,13 +43,13 @@ pub const Timer = enum(u1) {
     /// Enables or disables the interrupt for the given alarm.
     pub fn set_interrupt_enabled(timer: Timer, alarm: Alarm, enable: bool) void {
         const regs = timer.get_regs();
-        regs.INTE.write_raw(@as(u4, @intFromBool(enable)) << @intFromEnum(alarm));
+        regs.INTE.raw = @as(u4, @intFromBool(enable)) << @intFromEnum(alarm);
     }
 
     /// Clears the interrupt flag for the given alarm.
     pub fn clear_interrupt(timer: Timer, alarm: Alarm) void {
         const regs = timer.get_regs();
-        regs.INTR.write_raw(@as(u4, 1) << @intFromEnum(alarm));
+        regs.INTR.raw = @as(u4, 1) << @intFromEnum(alarm);
     }
 
     /// Schedules an alarm to be triggered when the low word of the timer
diff --git a/port/raspberrypi/rp2xxx/src/hal/uart.zig b/port/raspberrypi/rp2xxx/src/hal/uart.zig
index fcb96054e..51af19f35 100644
--- a/port/raspberrypi/rp2xxx/src/hal/uart.zig
+++ b/port/raspberrypi/rp2xxx/src/hal/uart.zig
@@ -5,10 +5,8 @@ const peripherals = microzig.chip.peripherals;
 const UART0_reg = peripherals.UART0;
 const UART1_reg = peripherals.UART1;
 
-const gpio = @import("gpio.zig");
 const clocks = @import("clocks.zig");
 const dma = @import("dma.zig");
-const resets = @import("resets.zig");
 const time = @import("time.zig");
 
 const UartRegs = microzig.chip.types.peripherals.UART0;
@@ -213,7 +211,7 @@ pub const UART = enum(u1) {
         });
         var tx_remaining = src.len;
         while (tx_remaining > 0 and uart.is_writeable()) {
-            uart_regs.UARTDR.write_raw(src[src.len - tx_remaining]);
+            uart_regs.UARTDR.raw = src[src.len - tx_remaining];
             tx_remaining -= 1;
         }
         uart_regs.UARTCR.modify(.{
@@ -306,7 +304,7 @@ pub const UART = enum(u1) {
                 while (!uart.is_writeable()) {
                     try deadline.check(time.get_time_since_boot());
                 }
-                uart_regs.UARTDR.write_raw(payload[offset]);
+                uart_regs.UARTDR.raw = payload[offset];
                 offset += 1;
             }
         }
diff --git a/port/raspberrypi/rp2xxx/src/hal/usb.zig b/port/raspberrypi/rp2xxx/src/hal/usb.zig
index 31747a31a..f4b99ad65 100644
--- a/port/raspberrypi/rp2xxx/src/hal/usb.zig
+++ b/port/raspberrypi/rp2xxx/src/hal/usb.zig
@@ -65,10 +65,10 @@ fn PerEndpoint(T: type) type {
 }
 
 // It would be nice to instead generate those arrays automatically with a regz patch.
-const BufferControlMmio = microzig.mmio.Mmio(@TypeOf(peripherals.USB_DPRAM.EP0_IN_BUFFER_CONTROL).underlying_type);
+const BufferControlMmio = @TypeOf(peripherals.USB_DPRAM.EP0_IN_BUFFER_CONTROL);
 const buffer_control: *volatile [16]PerEndpoint(BufferControlMmio) = @ptrCast(&peripherals.USB_DPRAM.EP0_IN_BUFFER_CONTROL);
 
-const EndpointControlMmio = microzig.mmio.Mmio(@TypeOf(peripherals.USB_DPRAM.EP1_IN_CONTROL).underlying_type);
+const EndpointControlMmio = @TypeOf(peripherals.USB_DPRAM.EP1_IN_CONTROL);
 const endpoint_control: *volatile [15]PerEndpoint(EndpointControlMmio) = @ptrCast(&peripherals.USB_DPRAM.EP1_IN_CONTROL);
 
 // +++++++++++++++++++++++++++++++++++++++++++++++++
@@ -182,17 +182,17 @@ pub fn Polled(config: Config) type {
 
             // Clear the control portion of DPRAM. This may not be necessary -- the
             // datasheet is ambiguous -- but the C examples do it, and so do we.
-            peripherals.USB_DPRAM.SETUP_PACKET_LOW.write_raw(0);
-            peripherals.USB_DPRAM.SETUP_PACKET_HIGH.write_raw(0);
+            peripherals.USB_DPRAM.SETUP_PACKET_LOW.raw = 0;
+            peripherals.USB_DPRAM.SETUP_PACKET_HIGH.raw = 0;
 
             for (1..config.max_endpoints_count) |i| {
-                endpoint_control[i - 1].in.write_raw(0);
-                endpoint_control[i - 1].out.write_raw(0);
+                endpoint_control[i - 1].in.raw = 0;
+                endpoint_control[i - 1].out.raw = 0;
             }
 
             for (0..config.max_endpoints_count) |i| {
-                buffer_control[i].in.write_raw(0);
-                buffer_control[i].out.write_raw(0);
+                buffer_control[i].in.raw = 0;
+                buffer_control[i].out.raw = 0;
             }
 
             // Mux the controller to the onboard USB PHY. I was surprised that there are
diff --git a/port/stmicro/stm32/src/hals/STM32L47X/lcd.zig b/port/stmicro/stm32/src/hals/STM32L47X/lcd.zig
index eef142bbc..53f24e1cc 100644
--- a/port/stmicro/stm32/src/hals/STM32L47X/lcd.zig
+++ b/port/stmicro/stm32/src/hals/STM32L47X/lcd.zig
@@ -2,11 +2,11 @@ const microzig = @import("microzig");
 
 const LCD = microzig.chip.peripherals.LCD;
 
-const LCD_COM_L = microzig.mmio.Mmio(packed struct(u32) {
+const LCD_COM_L = microzig.mmio.OldMmio(packed struct(u32) {
     SEG0T31: u32,
 });
 
-const LCD_COM_H = microzig.mmio.Mmio(packed struct(u32) {
+const LCD_COM_H = microzig.mmio.OldMmio(packed struct(u32) {
     SEG32T44: u12,
     reserved: u20,
 });
diff --git a/port/stmicro/stm32/src/hals/common/dma_common.zig b/port/stmicro/stm32/src/hals/common/dma_common.zig
index 24824048d..775880602 100644
--- a/port/stmicro/stm32/src/hals/common/dma_common.zig
+++ b/port/stmicro/stm32/src/hals/common/dma_common.zig
@@ -65,12 +65,12 @@ pub const Channel = struct {
         });
 
         if (config.mem_address) |address| {
-            self.reg_channel.MAR = address;
+            self.reg_channel.MAR.raw = address;
         }
         if (config.transfer_count) |count| {
             self.reg_channel.NDTR.modify_one("NDT", count);
         }
-        self.reg_channel.PAR = config.periph_address;
+        self.reg_channel.PAR.raw = config.periph_address;
     }
 
     pub fn start(self: *Self) void {
@@ -106,7 +106,7 @@ pub const Channel = struct {
         @memcpy(self.dma_buffer[0..buffer.len], buffer);
 
         self.reg_channel.NDTR.modify_one("NDT", @as(u16, @intCast(buffer.len)));
-        self.reg_channel.MAR = @intFromPtr(self.dma_buffer.ptr);
+        self.reg_channel.MAR.raw = @intFromPtr(self.dma_buffer.ptr);
     }
 
     /// Reads the number of remaining transfers.
diff --git a/port/stmicro/stm32/src/hals/common/gpio_v2.zig b/port/stmicro/stm32/src/hals/common/gpio_v2.zig
index fba4909f6..dae67f03e 100644
--- a/port/stmicro/stm32/src/hals/common/gpio_v2.zig
+++ b/port/stmicro/stm32/src/hals/common/gpio_v2.zig
@@ -136,7 +136,7 @@ pub const Pin = enum(usize) {
         const pin: u5 = @intCast(@intFromEnum(gpio) % 16);
         const modMask: u32 = gpio.mask_2bit();
 
-        port.PUPDR.write_raw((port.PUPDR.raw & ~modMask) | @as(u32, @intFromEnum(bias)) << (pin << 1));
+        port.PUPDR.raw = (port.PUPDR.raw & ~modMask) | @as(u32, @intFromEnum(bias)) << (pin << 1);
     }
 
     pub inline fn set_speed(gpio: Pin, speed: OSPEEDR) void {
@@ -144,7 +144,7 @@ pub const Pin = enum(usize) {
         const pin: u5 = @intCast(@intFromEnum(gpio) % 16);
         const modMask: u32 = gpio.mask_2bit();
 
-        port.OSPEEDR.write_raw((port.OSPEEDR.raw & ~modMask) | @as(u32, @intFromEnum(speed)) << (pin << 1));
+        port.OSPEEDR.raw = (port.OSPEEDR.raw & ~modMask) | @as(u32, @intFromEnum(speed)) << (pin << 1);
     }
 
     pub inline fn set_moder(gpio: Pin, moder: MODER) void {
@@ -152,14 +152,14 @@ pub const Pin = enum(usize) {
         const pin: u5 = @intCast(@intFromEnum(gpio) % 16);
         const modMask: u32 = gpio.mask_2bit();
 
-        port.MODER.write_raw((port.MODER.raw & ~modMask) | @as(u32, @intFromEnum(moder)) << (pin << 1));
+        port.MODER.raw = (port.MODER.raw & ~modMask) | @as(u32, @intFromEnum(moder)) << (pin << 1);
     }
 
     pub inline fn set_output_type(gpio: Pin, otype: OT) void {
         const port = gpio.get_port();
         const pin: u5 = @intCast(@intFromEnum(gpio) % 16);
 
-        port.OTYPER.write_raw((port.OTYPER.raw & ~gpio.mask()) | @as(u32, @intFromEnum(otype)) << pin);
+        port.OTYPER.raw = (port.OTYPER.raw & ~gpio.mask()) | @as(u32, @intFromEnum(otype)) << pin;
     }
 
     pub inline fn set_alternate_function(gpio: Pin, afr: AF) void {
@@ -167,7 +167,7 @@ pub const Pin = enum(usize) {
         const pin: u5 = @intCast(@intFromEnum(gpio) % 16);
         const afrMask: u32 = @as(u32, 0b1111) << ((pin % 8) << 2);
         const register = if (pin > 7) &port.AFR[1] else &port.AFR[0];
-        register.write_raw((register.raw & ~afrMask) | @as(u32, @intFromEnum(afr)) << ((pin % 8) << 2));
+        register.raw = (register.raw & ~afrMask) | @as(u32, @intFromEnum(afr)) << ((pin % 8) << 2);
     }
 
     pub fn from_port(port: Port, pin: u4) Pin {
diff --git a/port/stmicro/stm32/src/hals/common/i2c_v2.zig b/port/stmicro/stm32/src/hals/common/i2c_v2.zig
index 79951c469..eecdbd78f 100644
--- a/port/stmicro/stm32/src/hals/common/i2c_v2.zig
+++ b/port/stmicro/stm32/src/hals/common/i2c_v2.zig
@@ -4,7 +4,6 @@ const enums = @import("enums.zig");
 
 const I2C_Type = enums.I2C_Type;
 const I2C_Peripherals = microzig.chip.types.peripherals.i2c_v2.I2C;
-const peripherals = microzig.chip.peripherals;
 const hal = microzig.hal;
 const drivers = microzig.drivers.base;
 
@@ -124,7 +123,7 @@ const I2C = struct {
 
         regs.CR1.modify(.{ .PE = 0 });
 
-        regs.TIMINGR.modify(i2c.timingr);
+        regs.TIMINGR.write(i2c.timingr);
 
         regs.CR1.modify(.{ .PE = 1 });
     }
diff --git a/port/stmicro/stm32/src/hals/common/timer_v1.zig b/port/stmicro/stm32/src/hals/common/timer_v1.zig
index 5ba51079f..ffe3e1c9f 100644
--- a/port/stmicro/stm32/src/hals/common/timer_v1.zig
+++ b/port/stmicro/stm32/src/hals/common/timer_v1.zig
@@ -1,7 +1,6 @@
 const std = @import("std");
 const microzig = @import("microzig");
 const enums = @import("enums.zig");
-const periferals = microzig.chip.peripherals;
 
 const TIM_GP16 = microzig.chip.types.peripherals.timer_v1.TIM_GP16;
 const DIR = microzig.chip.types.peripherals.timer_v1.DIR;
@@ -188,7 +187,7 @@ pub const GPTimer = struct {
         //disable timer before configuring
         self.clear_configs();
         self.set_update_event(false); //disable update event to prevent unwanted updates
-        regs.PSC = config.prescaler;
+        regs.PSC.raw = config.prescaler;
         regs.ARR.modify(.{ .ARR = config.auto_reload });
         regs.CR1.modify(.{
             .CKD = config.clock_division,
diff --git a/port/texasinstruments/msp430/patches/msp430f5529.zon b/port/texasinstruments/msp430/patches/msp430f5529.zon
new file mode 100644
index 000000000..a0a4aca67
--- /dev/null
+++ b/port/texasinstruments/msp430/patches/msp430f5529.zon
@@ -0,0 +1,10 @@
+.{
+    .{ .add_struct_field = .{
+        .parent = "types.peripherals.Watchdog_Timer.WDTCTL",
+        .name = "WDTPW",
+        .size_bits = 8,
+        .offset_bits = 8,
+        .access = .write_only,
+        .type = .{ .uint = 8 },
+    } },
+}
diff --git a/port/texasinstruments/msp430/patches/msp430g2553.zon b/port/texasinstruments/msp430/patches/msp430g2553.zon
new file mode 100644
index 000000000..a0a4aca67
--- /dev/null
+++ b/port/texasinstruments/msp430/patches/msp430g2553.zon
@@ -0,0 +1,10 @@
+.{
+    .{ .add_struct_field = .{
+        .parent = "types.peripherals.Watchdog_Timer.WDTCTL",
+        .name = "WDTPW",
+        .size_bits = 8,
+        .offset_bits = 8,
+        .access = .write_only,
+        .type = .{ .uint = 8 },
+    } },
+}
diff --git a/port/texasinstruments/msp430/src/Chips.zig b/port/texasinstruments/msp430/src/Chips.zig
index 3e49d3694..659bcac3c 100644
--- a/port/texasinstruments/msp430/src/Chips.zig
+++ b/port/texasinstruments/msp430/src/Chips.zig
@@ -41,6 +41,10 @@ pub fn init(dep: *std.Build.Dependency) Self {
                 .{ .tag = .ram, .offset = 0x2400, .length = 0x2000, .access = .rwx },
                 .{ .name = "isr_vector", .tag = .none, .offset = 0xFF80, .length = 0x80, .access = .rx },
             },
+            // Adding patches here breaks building sorcerer 🤡
+            // .patch_files = &.{
+            //     b.path("patches/msp430f5529.zon"),
+            // },
         },
         .bundle_compiler_rt = false,
         .bundle_ubsan_rt = false,
@@ -73,6 +77,10 @@ pub fn init(dep: *std.Build.Dependency) Self {
                 .{ .tag = .ram, .offset = 0x200, .length = 0x200, .access = .rwx },
                 .{ .name = "isr_vector", .tag = .none, .offset = 0xFFE0, .length = 0x20, .access = .rx },
             },
+            // Adding patches here breaks building sorcerer 🤡
+            // .patch_files = &.{
+            //     b.path("patches/msp430g2553.zon"),
+            // },
         },
         .bundle_compiler_rt = false,
         .bundle_ubsan_rt = false,
diff --git a/port/texasinstruments/msp430/src/hal/watchdog.zig b/port/texasinstruments/msp430/src/hal/watchdog.zig
index 10d05c842..bb1cd249b 100644
--- a/port/texasinstruments/msp430/src/hal/watchdog.zig
+++ b/port/texasinstruments/msp430/src/hal/watchdog.zig
@@ -4,7 +4,6 @@ const WDTCTL = &microzig.chip.peripherals.Watchdog_Timer.WDTCTL;
 pub fn disable() void {
     WDTCTL.modify(.{
         .WDTHOLD = 1,
-        // This needs to be patched
-        .padding = 0x5A,
+        .WDTPW = 0x5A,
     });
 }
diff --git a/port/wch/ch32v/src/cpus/qingkev2-rv32ec.zig b/port/wch/ch32v/src/cpus/qingkev2-rv32ec.zig
index 7ae681cee..227a6dc79 100644
--- a/port/wch/ch32v/src/cpus/qingkev2-rv32ec.zig
+++ b/port/wch/ch32v/src/cpus/qingkev2-rv32ec.zig
@@ -69,7 +69,6 @@ pub inline fn system_init(comptime chip: anytype) void {
     // RCC->CFGR0 &= (uint32_t)0xF8FF0000;
     RCC.CFGR0.modify(.{
         .SW = 0,
-        .SWS = 0,
         .HPRE = 0,
         .ADCPRE = 0,
         .MCO = 0,
diff --git a/port/wch/ch32v/src/cpus/qingkev3-rv32imac.zig b/port/wch/ch32v/src/cpus/qingkev3-rv32imac.zig
index e839eb843..7d1b45a33 100644
--- a/port/wch/ch32v/src/cpus/qingkev3-rv32imac.zig
+++ b/port/wch/ch32v/src/cpus/qingkev3-rv32imac.zig
@@ -102,7 +102,6 @@ pub inline fn system_init(comptime chip: anytype) void {
     // RCC->CFGR0 &= (uint32_t)0xF8FF0000;
     RCC.CFGR0.modify(.{
         .SW = 0,
-        .SWS = 0,
         .HPRE = 0,
         .ADCPRE = 0,
         .MCO = 0,
diff --git a/port/wch/ch32v/src/cpus/qingkev4-rv32imac.zig b/port/wch/ch32v/src/cpus/qingkev4-rv32imac.zig
index c0e246b8b..aceba604e 100644
--- a/port/wch/ch32v/src/cpus/qingkev4-rv32imac.zig
+++ b/port/wch/ch32v/src/cpus/qingkev4-rv32imac.zig
@@ -164,7 +164,6 @@ pub inline fn system_init(comptime chip: anytype) void {
     // RCC->CFGR0 &= (uint32_t)0xF0FF0000;
     RCC.CFGR0.modify(.{
         .SW = 0,
-        .SWS = 0,
         .HPRE = 0,
         .PPRE1 = 0,
         .PPRE2 = 0,
diff --git a/port/wch/ch32v/src/cpus/qingkev4-rv32imacf.zig b/port/wch/ch32v/src/cpus/qingkev4-rv32imacf.zig
index e64dbbb1b..fe4228a31 100644
--- a/port/wch/ch32v/src/cpus/qingkev4-rv32imacf.zig
+++ b/port/wch/ch32v/src/cpus/qingkev4-rv32imacf.zig
@@ -204,7 +204,6 @@ pub inline fn system_init(comptime chip: anytype) void {
     // RCC->CFGR0 &= (uint32_t)0xF0FF0000;
     RCC.CFGR0.modify(.{
         .SW = 0,
-        .SWS = 0,
         .HPRE = 0,
         .PPRE1 = 0,
         .PPRE2 = 0,
diff --git a/port/wch/ch32v/src/hals/dma.zig b/port/wch/ch32v/src/hals/dma.zig
index 32687c725..ac8515a49 100644
--- a/port/wch/ch32v/src/hals/dma.zig
+++ b/port/wch/ch32v/src/hals/dma.zig
@@ -5,7 +5,6 @@
 //!
 //!
 const std = @import("std");
-const assert = std.debug.assert;
 
 const microzig = @import("microzig");
 const mdf = microzig.drivers;
@@ -227,7 +226,7 @@ pub const Channel = enum(u3) {
         // Clear all interrupt flags for this channel. There are four interrupts per channel, so we
         // shift by 4 * (channel - 1). Channel enum is 1-indexed, so subtract 1 for bit position.
         const flag_shift: u5 = (@as(u5, @intFromEnum(chan)) - 1) * 4;
-        regs.INTFCR.write_raw(@as(u32, 0b1111) << flag_shift);
+        regs.INTFCR.raw = @as(u32, 0b1111) << flag_shift;
 
         // NOTE: DIR bit affects transfer direction even in MEM2MEM mode (undocumented behavior):
         // - Always place the peripheral address in PADDR when a peripheral is involved.
@@ -239,14 +238,14 @@ pub const Channel = enum(u3) {
         //     Periph→Mem:  PADDR=read (periph),  MADDR=write (memory), DIR=0
         //     Mem→Mem:     PADDR=read (source),  MADDR=write (dest),   DIR=0
         if (H.is_peripheral(WriteType)) {
-            regs.MADDR.write_raw(read_addr);
-            regs.PADDR.write_raw(write_addr);
+            regs.MADDR.raw = read_addr;
+            regs.PADDR.raw = write_addr;
         } else {
-            regs.MADDR.write_raw(write_addr);
-            regs.PADDR.write_raw(read_addr);
+            regs.MADDR.raw = write_addr;
+            regs.PADDR.raw = read_addr;
         }
         // Set the amount of data to transfer
-        regs.CNTR.write_raw(count);
+        regs.CNTR.raw = count;
         // Set the priority
         regs.CFGR.modify(.{ .PL = @intFromEnum(config.priority) });
         // Set the rest of the config
@@ -323,7 +322,8 @@ pub const Channel = enum(u3) {
     pub fn clear_complete_flag(comptime chan: Channel) void {
         const regs = chan.get_regs();
         const flag_shift: u5 = (@as(u5, @intFromEnum(chan)) - 1) * 4;
-        regs.INTFCR.write_raw(@as(u32, 0b0010) << flag_shift); // Clear only TCIF
+        // Why not use the underlying struct?
+        regs.INTFCR.raw = @as(u32, 0b0010) << flag_shift; // Clear only TCIF
     }
 
     pub fn get_remaining_count(comptime chan: Channel) u16 {
diff --git a/port/wch/ch32v/src/hals/i2c.zig b/port/wch/ch32v/src/hals/i2c.zig
index 62f18a5a5..d4c29be4e 100644
--- a/port/wch/ch32v/src/hals/i2c.zig
+++ b/port/wch/ch32v/src/hals/i2c.zig
@@ -4,7 +4,6 @@
 //! Based on the WCH CH32V20x I2C peripheral implementation.
 //! Reference: CH32V20x Reference Manual Section on I2C
 //!
-const std = @import("std");
 const microzig = @import("microzig");
 const mdf = microzig.drivers;
 const drivers = mdf.base;
@@ -178,7 +177,7 @@ pub const I2C = enum(u1) {
         }
 
         // Write clock configuration
-        regs.CKCFGR.write_raw(ccr);
+        regs.CKCFGR.raw = ccr;
 
         // Enable peripheral first
         i2c.enable();
@@ -231,7 +230,7 @@ pub const I2C = enum(u1) {
     /// Send 7-bit address with direction bit
     inline fn send_address(i2c: I2C, addr: Address, direction: enum { write, read }) void {
         const addr_byte = @as(u8, @intFromEnum(addr)) << 1 | @intFromBool(direction == .read);
-        i2c.get_regs().DATAR.write_raw(addr_byte);
+        i2c.get_regs().DATAR.raw = addr_byte;
     }
 
     /// Common wait for STAR1/STAR2 flag with timeout
@@ -330,7 +329,7 @@ pub const I2C = enum(u1) {
             try i2c.wait_flag_star1("TxE", 1, deadline);
 
             // Write data to DATAR
-            regs.DATAR.write_raw(element.value);
+            regs.DATAR.raw = element.value;
         }
 
         // Wait for BTF (Byte Transfer Finished) - ensures last byte is transmitted
diff --git a/port/wch/ch32v/src/hals/usart.zig b/port/wch/ch32v/src/hals/usart.zig
index f71655363..d796815c4 100644
--- a/port/wch/ch32v/src/hals/usart.zig
+++ b/port/wch/ch32v/src/hals/usart.zig
@@ -242,7 +242,7 @@ pub const USART = enum(u2) {
         const fraction = ((fraction_part * 16 + 50) / 100) & 0x0F;
 
         const brr_value = (mantissa << 4) | fraction;
-        regs.BRR.write_raw(@intCast(brr_value));
+        regs.BRR.raw = @intCast(brr_value);
     }
 
     /// Check if transmit data register is empty (can write)
@@ -262,7 +262,7 @@ pub const USART = enum(u2) {
 
     /// Write a single byte (non-blocking)
     pub inline fn write_byte(usart: USART, byte: u8) void {
-        usart.get_regs().DATAR.write_raw(byte);
+        usart.get_regs().DATAR.raw = byte;
     }
 
     /// Read a single byte (non-blocking)
diff --git a/tools/regz/build.zig b/tools/regz/build.zig
index 1570f018b..27d7eb64a 100644
--- a/tools/regz/build.zig
+++ b/tools/regz/build.zig
@@ -1,8 +1,5 @@
 const std = @import("std");
 const Build = std.Build;
-const Compile = Build.Compile;
-const Step = Build.Step;
-const GeneratedFile = Build.GeneratedFile;
 
 pub const patch = @import("src/patch.zig");
 
@@ -10,25 +7,22 @@ pub fn build(b: *Build) !void {
     const target = b.standardTargetOptions(.{});
     const optimize = b.standardOptimizeOption(.{});
 
-    const libxml2_dep = b.dependency("libxml2", .{
+    // Dependencies
+
+    const libxml2 = b.dependency("libxml2", .{
         .target = target,
         .optimize = .ReleaseSafe,
         .iconv = false,
-    });
+    })
+        .artifact("xml2");
 
-    const sqlite3_dep = b.dependency("sqlite3", .{
+    const zqlite = b.dependency("zqlite", .{
         .target = target,
         .optimize = .ReleaseSafe,
-    });
-    const sqlite3_lib = sqlite3_dep.artifact("sqlite3");
-
-    const zqlite_dep = b.dependency("zqlite", .{
-        .target = target,
-        .optimize = optimize,
-    });
+    })
+        .module("zqlite");
 
-    const zqlite = zqlite_dep.module("zqlite");
-    zqlite.linkLibrary(sqlite3_lib);
+    // Main executable
 
     const regz = b.addExecutable(.{
         .name = "regz",
@@ -36,41 +30,46 @@ pub fn build(b: *Build) !void {
             .root_source_file = b.path("src/main.zig"),
             .target = target,
             .optimize = optimize,
+            .imports = &.{
+                .{ .name = "zqlite", .module = zqlite },
+            },
         }),
-        .use_llvm = true,
     });
-    regz.linkLibrary(libxml2_dep.artifact("xml2"));
-    regz.root_module.addImport("zqlite", zqlite);
-    b.installArtifact(regz);
+    regz.linkLibrary(libxml2);
 
-    const exported_module = b.addModule("regz", .{
-        .root_source_file = b.path("src/module.zig"),
-    });
-    exported_module.linkLibrary(libxml2_dep.artifact("xml2"));
-    exported_module.addImport("zqlite", zqlite);
+    b.installArtifact(regz);
 
     const run_cmd = b.addRunArtifact(regz);
     run_cmd.step.dependOn(b.getInstallStep());
-    if (b.args) |args| {
+    if (b.args) |args|
         run_cmd.addArgs(args);
-    }
+    b.step("run", "Run the app").dependOn(&run_cmd.step);
 
-    const run_step = b.step("run", "Run the app");
-    run_step.dependOn(&run_cmd.step);
+    // Library
+
+    const exported_module = b.addModule("regz", .{
+        .root_source_file = b.path("src/root.zig"),
+        .imports = &.{
+            .{ .name = "zqlite", .module = zqlite },
+        },
+    });
+    exported_module.linkLibrary(libxml2);
+
+    // Tests
 
     const tests = b.addTest(.{
         .root_module = b.createModule(.{
-            .root_source_file = b.path("src/Database.zig"),
+            .root_source_file = b.path("src/main.zig"),
             .target = target,
             .optimize = optimize,
+            .imports = &.{
+                .{ .name = "zqlite", .module = zqlite },
+            },
         }),
-        .use_llvm = true,
     });
-    tests.linkLibrary(libxml2_dep.artifact("xml2"));
-    tests.root_module.addImport("zqlite", zqlite);
+    tests.linkLibrary(libxml2);
     tests.step.dependOn(&regz.step);
 
     const run_tests = b.addRunArtifact(tests);
-    const test_step = b.step("test", "Run unit tests");
-    test_step.dependOn(&run_tests.step);
+    b.step("test", "Run unit tests").dependOn(&run_tests.step);
 }
diff --git a/tools/regz/build.zig.zon b/tools/regz/build.zig.zon
index 154dc6eaa..bdb2a6424 100644
--- a/tools/regz/build.zig.zon
+++ b/tools/regz/build.zig.zon
@@ -13,10 +13,6 @@
             .url = "git+https://github.com/mattnite/zig-build-libxml2.git#5474281ad4d173ed298ee789c7dce4f5edb78e10",
             .hash = "libxml2-0.0.0-Kr0Y1Ac4ngAiRuFTS2qMO9j-KZsD0PKFKKXoZjynTHLq",
         },
-        .sqlite3 = .{
-            .url = "git+https://github.com/allyourcodebase/sqlite3#8f840560eae88ab66668c6827c64ffbd0d74ef37",
-            .hash = "sqlite3-3.51.0-DMxLWssOAABZ8cAvU_LfBIbp0kZjm824PU8sSLXpEDdr",
-        },
         .zqlite = .{
             .url = "git+https://github.com/karlseguin/zqlite.zig#b44ed5cdc64859b08446c246f307e65ebe2b2d9c",
             .hash = "zqlite-0.0.0-RWLaY_y_mADh2LdbDrG_2HT2dBAcsAR8Jig_7-dOJd0B",
diff --git a/tools/regz/src/Database.zig b/tools/regz/src/Database.zig
index d9d751d27..22b941d8f 100644
--- a/tools/regz/src/Database.zig
+++ b/tools/regz/src/Database.zig
@@ -1,28 +1,24 @@
-gpa: Allocator,
-conn: zqlite.Conn,
-
-const Database = @This();
 const std = @import("std");
 const Allocator = std.mem.Allocator;
 const assert = std.debug.assert;
+const log = std.log.scoped(.db);
+
+const file_size_max = 100 * 1024 * 1024;
 
+const Database = @This();
+
+const Arch = @import("arch.zig").Arch;
+const Patch = @import("patch.zig").Patch;
 const zqlite = @import("zqlite");
-const c = zqlite.c;
 
+const atdf = @import("format/atdf.zig");
+const embassy = @import("format/embassy.zig");
+const svd = @import("format/svd.zig");
+const targetdb = @import("format/targetdb.zig");
 const xml = @import("xml.zig");
-const svd = @import("svd.zig");
-const atdf = @import("atdf.zig");
-const embassy = @import("embassy.zig");
-const targetdb = @import("targetdb.zig");
-const gen = @import("gen.zig");
-const analysis = @import("analysis.zig");
-const Patch = @import("patch.zig").Patch;
-const SQL_Options = @import("SQL_Options.zig");
-const Arch = @import("arch.zig").Arch;
-pub const Directory = @import("Directory.zig");
 
-const log = std.log.scoped(.db);
-const file_size_max = 100 * 1024 * 1024;
+gpa: Allocator,
+conn: zqlite.Conn,
 
 // Actual instances will have "Instance" in the type name for the ID
 pub const DeviceID = ID(u32, "devices");
@@ -36,6 +32,43 @@ pub const RegisterID = ID(u32, "registers");
 pub const ModeID = ID(u32, "modes");
 pub const StructID = ID(u32, "structs");
 
+const SQL_Options = struct {
+    primary_key: ?PrimaryKey = null,
+    foreign_keys: []const ForeignKey = &.{},
+    unique_constraints: []const Unique = &.{},
+
+    pub const Unique = []const []const u8;
+
+    pub const PrimaryKey = struct {
+        name: []const u8,
+        autoincrement: bool = false,
+    };
+
+    pub const On = enum {
+        no_action,
+        restrict,
+        cascade,
+        set_null,
+        set_default,
+
+        pub fn to_string(on: On) []const u8 {
+            return switch (on) {
+                .no_action => "NO ACTION",
+                .restrict => "RESTRICT",
+                .cascade => "CASCADE",
+                .set_null => "SET NULL",
+                .set_default => "SET DEFAULT",
+            };
+        }
+    };
+
+    pub const ForeignKey = struct {
+        name: []const u8,
+        on_delete: On = .no_action,
+        on_update: On = .no_action,
+    };
+};
+
 pub const Device = struct {
     id: DeviceID,
     name: []const u8,
@@ -355,17 +388,82 @@ pub const Access = enum {
     read_write,
     read_only,
     write_only,
-    write_once,
-    read_write_once,
+    writeonce,
+    read_writeonce,
+    // Read normal, write 1 to clear
+    read_clear,
+    // Has one of known ambiguous names, needs a patch
+    ambiguous,
+
+    const names = .{
+        .read_write = .{"read-write"},
+        .read_only = .{"read-only"},
+        .write_only = .{"write-only"},
+        .writeonce = .{"writeonce"},
+        .read_writeonce = .{"read-writeonce"},
+        .read_clear = .{"read/clear"},
+        .ambiguous = .{"write"},
+    };
+
+    const names_short = .{
+        .read_write = .{ "RW", "R/W" },
+        .read_only = .{"R"},
+        .write_only = .{"W"},
+    };
 
     pub const BaseType = []const u8;
-    pub const default = .read_write;
+    pub const default: @This() = .read_write;
 
-    pub fn to_string(access: Access) []const u8 {
-        return inline for (@typeInfo(Access).@"enum".fields) |field| {
-            if (@field(Access, field.name) == access)
-                break field.name;
-        } else unreachable;
+    pub fn try_parse(str: []const u8) ?@This() {
+        inline for (@typeInfo(@TypeOf(names)).@"struct".fields) |field| {
+            inline for (@field(names, field.name)) |name| {
+                if (std.ascii.eqlIgnoreCase(name, str))
+                    return @field(@This(), field.name);
+            }
+        }
+        return null;
+    }
+
+    pub fn parse(str: []const u8) @This() {
+        return try_parse(str) orelse {
+            const fmt = comptime blk: {
+                var ret: []const u8 = "Failed to parse access string '{s}', expected one of ";
+                for (@typeInfo(@TypeOf(names)).@"struct".fields) |field| {
+                    for (@field(names, field.name)) |name|
+                        ret = ret ++ "'" ++ name ++ "', ";
+                }
+                break :blk ret;
+            };
+            std.debug.panic(fmt, .{str});
+        };
+    }
+
+    pub fn try_parse_short(str: []const u8) ?@This() {
+        inline for (@typeInfo(@TypeOf(names_short)).@"struct".fields) |field| {
+            inline for (@field(names_short, field.name)) |name| {
+                if (std.mem.eql(u8, name, str))
+                    return @field(@This(), field.name);
+            }
+        }
+        return null;
+    }
+
+    pub fn parse_short(str: []const u8) @This() {
+        return try_parse_short(str) orelse {
+            const fmt = comptime blk: {
+                var ret: []const u8 = "Failed to parse access string '{s}', expected one of ";
+                for (@typeInfo(@TypeOf(names_short)).@"struct".fields) |field| {
+                    for (@field(names_short, field.name)) |name|
+                        ret = ret ++ "'" ++ name ++ "', ";
+                }
+                break :blk ret;
+            };
+            std.debug.panic(fmt, .{str});
+        };
+    }
+
+    pub fn to_string(self: @This()) []const u8 {
+        return @tagName(self);
     }
 };
 
@@ -599,7 +697,7 @@ pub fn destroy(db: *Database) void {
 pub fn create_from_doc(allocator: Allocator, format: Format, doc: xml.Doc) !*Database {
     var db = try Database.create(allocator);
     errdefer {
-        std.log.err("sqlite: {s}", .{db.conn.lastError()});
+        log.err("sqlite: {s}", .{db.conn.lastError()});
         db.destroy();
     }
 
@@ -617,7 +715,7 @@ pub fn create_from_path(allocator: Allocator, format: Format, path: []const u8,
         .embassy => blk: {
             var db = try Database.create(allocator);
             errdefer {
-                std.log.err("sqlite: {s}", .{db.conn.lastError()});
+                log.err("sqlite: {s}", .{db.conn.lastError()});
                 db.destroy();
             }
 
@@ -627,7 +725,7 @@ pub fn create_from_path(allocator: Allocator, format: Format, path: []const u8,
         .targetdb => blk: {
             var db = try Database.create(allocator);
             errdefer {
-                std.log.err("sqlite: {s}", .{db.conn.lastError()});
+                log.err("sqlite: {s}", .{db.conn.lastError()});
                 db.destroy();
             }
 
@@ -982,7 +1080,7 @@ pub fn get_nested_struct_fields_with_calculated_size(
 
         var depth: u8 = 0;
         const size_bytes = try db.recursively_calculate_struct_size(&depth, &size_cache, gpa, nsf.struct_id);
-        std.log.debug("Calculated struct size: struct_id={f} size_bytes={}", .{ nsf.struct_id, size_bytes });
+        log.debug("Calculated struct size: struct_id={f} size_bytes={}", .{ nsf.struct_id, size_bytes });
         nsf.size_bytes = if (size_bytes > 0) size_bytes else continue;
         try ret.append(gpa, nsf.*);
     }
@@ -1169,10 +1267,10 @@ pub fn backup(db: *Database, path: [:0]const u8) !void {
     const backup_db = try zqlite.open(path, flags);
     defer backup_db.close();
 
-    const backup_step = c.sqlite3_backup_init(@ptrCast(backup_db.conn), "main", @ptrCast(db.conn.conn), "main");
+    const backup_step = zqlite.c.sqlite3_backup_init(@ptrCast(backup_db.conn), "main", @ptrCast(db.conn.conn), "main");
     if (backup_step != null) {
-        _ = c.sqlite3_backup_step(backup_step, -1);
-        _ = c.sqlite3_backup_finish(backup_step);
+        _ = zqlite.c.sqlite3_backup_step(backup_step, -1);
+        _ = zqlite.c.sqlite3_backup_finish(backup_step);
     }
 }
 
@@ -1597,7 +1695,7 @@ pub const CreatePeripheralOptions = struct {
 /// The code generated for a peripheral can be a struct itself, or a namespace
 /// containing structs. In the latter case, a peripheral
 pub fn create_peripheral(db: *Database, opts: CreatePeripheralOptions) !PeripheralID {
-    errdefer std.log.err("sqlite: {s}", .{db.conn.lastError()});
+    errdefer log.err("sqlite: {s}", .{db.conn.lastError()});
 
     try db.conn.transaction();
     errdefer db.conn.rollback();
@@ -1711,7 +1809,7 @@ pub const CreateRegisterOptions = struct {
     size_bits: u64,
     /// count if there is an array
     count: ?u64 = null,
-    access: Access = .read_write,
+    access: Access = .default,
     reset_mask: ?u64 = null,
     reset_value: ?u64 = null,
 };
@@ -1936,19 +2034,10 @@ pub fn struct_is_zero_sized(db: *Database, allocator: Allocator, struct_id: Stru
 /// Returns the last part of the reference, and the beginning part of the
 /// reference
 fn get_ref_last_component(ref: []const u8) !struct { []const u8, ?[]const u8 } {
-    var it = std.mem.splitScalar(u8, ref, '.');
-    var last: ?[]const u8 = null;
-    while (it.next()) |comp| {
-        last = comp;
-    }
-
-    return if (last) |l|
-        if (l.len == ref.len)
-            .{ l, null }
-        else
-            .{ l, ref[0 .. ref.len - l.len - 1] }
+    if (std.mem.lastIndexOfScalar(u8, ref, '.')) |pos|
+        return .{ ref[pos + 1 ..], ref[0..pos] }
     else
-        error.EmptyRef;
+        return .{ ref, null };
 }
 
 fn strip_ref_prefix(expected_prefix: []const u8, ref: []const u8) ![]const u8 {
@@ -1972,30 +2061,41 @@ fn get_struct_ref(db: *Database, ref: []const u8) !StructID {
 
     const base_ref = try strip_ref_prefix("types.peripherals", ref);
     const struct_name, const rest_ref = try get_ref_last_component(base_ref);
-    return if (rest_ref) |rest| blk: {
-        var it = std.mem.splitScalar(u8, rest, '.');
-        const peripheral_name = it.next() orelse return error.NoPeripheral;
-        const peripheral_id = try db.get_peripheral_by_name(peripheral_name) orelse return error.NoPeripheral;
-        var struct_id = try db.get_peripheral_struct(peripheral_id);
-        if (it.index == null) {
-            return if (std.mem.eql(u8, struct_name, peripheral_name))
-                struct_id
-            else
-                error.NoPeripheral;
-        }
-
-        break :blk while (it.next()) |name| {
-            const struct_decl = try db.get_struct_decl_by_name(arena.allocator(), struct_id, name);
-            if (it.index == null and std.mem.eql(u8, struct_name, struct_decl.name))
-                break struct_decl.struct_id;
 
-            struct_id = struct_decl.struct_id;
-        } else error.RefNotFound;
-    } else blk: {
+    const rest = rest_ref orelse {
         // just getting a peripheral
-        const peripheral_id = try db.get_peripheral_by_name(struct_name) orelse return error.NoPeripheral;
-        break :blk try db.get_peripheral_struct(peripheral_id);
+        const peripheral_id = try db.get_peripheral_by_name(struct_name) orelse
+            return error.NoPeripheral;
+        return try db.get_peripheral_struct(peripheral_id);
+    };
+
+    var it = std.mem.splitScalar(u8, rest, '.');
+    const peripheral_name = it.first();
+
+    const peripheral_id = try db.get_peripheral_by_name(peripheral_name) orelse {
+        log.warn("No peripheral named '{s}' found", .{peripheral_name});
+        return error.NoPeripheral;
     };
+
+    var struct_id = try db.get_peripheral_struct(peripheral_id);
+    if (it.index == null) {
+        if (std.mem.eql(u8, struct_name, peripheral_name))
+            return struct_id
+        else {
+            log.warn("Expected struct '{s}', got '{s}'", .{ struct_name, peripheral_name });
+            return error.NoPeripheral;
+        }
+    }
+
+    while (it.next()) |name| {
+        const struct_decl = try db.get_struct_decl_by_name(arena.allocator(), struct_id, name);
+        struct_id = struct_decl.struct_id;
+
+        if (it.index == null and std.mem.eql(u8, struct_name, struct_decl.name))
+            return struct_id;
+    }
+
+    return error.RefNotFound;
 }
 
 fn get_enum_ref(db: *Database, ref: []const u8) !EnumID {
@@ -2016,6 +2116,7 @@ fn get_register_ref(db: *Database, ref: []const u8) !RegisterID {
 
     const register_name, const struct_ref = try get_ref_last_component(ref);
     const struct_id = try db.get_struct_ref(struct_ref orelse return error.InvalidRef);
+
     const register = try db.get_register_by_name(arena.allocator(), struct_id, register_name);
     return register.id;
 }
@@ -2054,126 +2155,126 @@ fn cleanup_unused_enums(db: *Database) !void {
     , .{});
 }
 
-pub fn apply_patch(db: *Database, zon_text: [:0]const u8, diags: *std.zon.parse.Diagnostics) !void {
-    const patches = try std.zon.parse.fromSlice([]const Patch, db.gpa, zon_text, diags, .{});
-    defer std.zon.parse.free(db.gpa, patches);
-
-    for (patches) |patch| {
-        switch (patch) {
-            .override_arch => |override_arch| {
-                const device_id = try db.get_device_id_by_name(override_arch.device_name) orelse {
-                    return error.DeviceNotFound;
-                };
-
-                try db.conn.exec(
-                    \\UPDATE devices
-                    \\SET arch = ?
-                    \\WHERE id = ?;
-                , .{
-                    override_arch.arch.to_string(),
-                    @intFromEnum(device_id),
-                });
-            },
-            .set_device_property => |set_prop| {
-                const device_id = try db.get_device_id_by_name(set_prop.device_name) orelse {
-                    return error.DeviceNotFound;
-                };
-
-                try db.conn.exec(
-                    \\INSERT INTO device_properties
-                    \\  (device_id, key, value, description)
-                    \\VALUES
-                    \\  (?, ?, ?, ?)
-                    \\ON CONFLICT(device_id, key)
-                    \\DO UPDATE SET
-                    \\  value = excluded.value,
-                    \\  description = excluded.description;
-                , .{
-                    @intFromEnum(device_id),
-                    set_prop.key,
-                    set_prop.value,
-                    set_prop.description,
-                });
-            },
-            .add_enum => |add_enum| {
-                const struct_id = try db.get_struct_ref(add_enum.parent);
+pub fn apply_patch(db: *Database, patch: Patch) !void {
+    switch (patch) {
+        .override_arch => |override_arch| {
+            const device_id = try db.get_device_id_by_name(override_arch.device_name) orelse {
+                return error.DeviceNotFound;
+            };
+
+            try db.conn.exec(
+                \\UPDATE devices
+                \\SET arch = ?
+                \\WHERE id = ?;
+            , .{
+                override_arch.arch.to_string(),
+                @intFromEnum(device_id),
+            });
+        },
+        .set_device_property => |set_prop| {
+            const device_id = try db.get_device_id_by_name(set_prop.device_name) orelse {
+                return error.DeviceNotFound;
+            };
+
+            try db.conn.exec(
+                \\INSERT INTO device_properties
+                \\  (device_id, key, value, description)
+                \\VALUES
+                \\  (?, ?, ?, ?)
+                \\ON CONFLICT(device_id, key)
+                \\DO UPDATE SET
+                \\  value = excluded.value,
+                \\  description = excluded.description;
+            , .{
+                @intFromEnum(device_id),
+                set_prop.key,
+                set_prop.value,
+                set_prop.description,
+            });
+        },
+        .add_type => |add_type| {
+            const struct_id = try db.get_struct_ref(add_type.parent);
+            _ = try db.add_type_helper(struct_id, add_type.type_name, add_type.type);
+        },
+        .set_enum_type => |set_enum_type| {
+            const enum_id = if (set_enum_type.to) |to| try db.get_enum_ref(to) else null;
+            const field_name, const register_ref = try get_ref_last_component(set_enum_type.of);
+            const register_id = try db.get_register_ref(register_ref orelse return error.InvalidRef);
+            try db.set_register_field_enum_id(register_id, field_name, enum_id);
+            try db.cleanup_unused_enums();
+        },
+        .add_interrupt => |add_interrupt| {
+            const device_id = try db.get_device_id_by_name(add_interrupt.device_name) orelse {
+                return error.DeviceNotFound;
+            };
+
+            _ = try db.create_interrupt(device_id, .{
+                .name = add_interrupt.name,
+                .description = add_interrupt.description,
+                .idx = add_interrupt.idx,
+            });
+        },
+        .add_type_and_apply => |add_type_patch| {
+            // First, create the enum (same as add_enum)
+            const struct_id = try db.get_struct_ref(add_type_patch.parent);
 
-                const enum_id = try db.create_enum(struct_id, .{
-                    .name = add_enum.@"enum".name,
-                    .description = add_enum.@"enum".description,
-                    .size_bits = add_enum.@"enum".bitsize,
-                });
+            const type_id = try db.add_type_helper(struct_id, add_type_patch.type_name, add_type_patch.type);
 
-                for (add_enum.@"enum".fields) |enum_field| {
-                    try db.add_enum_field(enum_id, .{
-                        .name = enum_field.name,
-                        .description = enum_field.description,
-                        .value = enum_field.value,
-                    });
-                }
-            },
-            .set_enum_type => |set_enum_type| {
-                const enum_id = if (set_enum_type.to) |to| try db.get_enum_ref(to) else null;
-                const field_name, const register_ref = try get_ref_last_component(set_enum_type.of);
+            // Then, apply to all specified fields (same as set_enum_type)
+            for (add_type_patch.apply_to) |field_ref| {
+                const field_name, const register_ref = try get_ref_last_component(field_ref);
                 const register_id = try db.get_register_ref(register_ref orelse return error.InvalidRef);
-                try db.set_register_field_enum_id(register_id, field_name, enum_id);
-                try db.cleanup_unused_enums();
-            },
-            .add_interrupt => |add_interrupt| {
-                const device_id = try db.get_device_id_by_name(add_interrupt.device_name) orelse {
-                    return error.DeviceNotFound;
-                };
-
-                _ = try db.create_interrupt(device_id, .{
-                    .name = add_interrupt.name,
-                    .description = add_interrupt.description,
-                    .idx = add_interrupt.idx,
-                });
-            },
-            .add_enum_and_apply => |add_enum_patch| {
-                // First, create the enum (same as add_enum)
-                const struct_id = try db.get_struct_ref(add_enum_patch.parent);
-
-                const enum_id = try db.create_enum(struct_id, .{
-                    .name = add_enum_patch.@"enum".name,
-                    .description = add_enum_patch.@"enum".description,
-                    .size_bits = add_enum_patch.@"enum".bitsize,
-                });
-
-                for (add_enum_patch.@"enum".fields) |enum_field| {
-                    try db.add_enum_field(enum_id, .{
-                        .name = enum_field.name,
-                        .description = enum_field.description,
-                        .value = enum_field.value,
-                    });
-                }
-
-                // Then, apply to all specified fields (same as set_enum_type)
-                for (add_enum_patch.apply_to) |field_ref| {
-                    const field_name, const register_ref = try get_ref_last_component(field_ref);
-                    const register_id = try db.get_register_ref(register_ref orelse return error.InvalidRef);
-                    try db.set_register_field_enum_id(register_id, field_name, enum_id);
-                }
-            },
-        }
+                try db.set_register_field_enum_id(register_id, field_name, type_id);
+            }
+        },
+        .add_struct_field => |opts| {
+            var arena = std.heap.ArenaAllocator.init(db.gpa);
+            defer arena.deinit();
+
+            const enum_id, const size_bits = switch (opts.type) {
+                .@"enum" => |ref| blk: {
+                    const id = try db.get_enum_ref(ref);
+                    const e = try db.get_enum(arena.allocator(), id);
+                    break :blk .{ id, e.size_bits };
+                },
+                .uint => |bits| .{ null, bits },
+            };
+            const reg_id = try db.get_register_ref(opts.parent);
+            try db.add_register_field(reg_id, .{
+                .name = opts.name,
+                .description = opts.description,
+                .size_bits = size_bits,
+                .offset_bits = opts.offset_bits,
+                .enum_id = enum_id,
+                .access = opts.access,
+            });
+        },
     }
 }
 
-pub const ToZigOptions = gen.ToZigOptions;
-
-pub fn to_zig(db: *Database, output_dir: Directory, opts: ToZigOptions) !void {
-    try gen.to_zig(db, output_dir, opts);
-}
+fn add_type_helper(db: *Database, parent: StructID, name: []const u8, @"type": Patch.Type) !EnumID {
+    switch (@"type") {
+        .@"enum" => |info| {
+            const enum_id = try db.create_enum(parent, .{
+                .name = name,
+                .description = info.description,
+                .size_bits = info.bitsize,
+            });
+
+            for (info.fields) |enum_field| {
+                try db.add_enum_field(enum_id, .{
+                    .name = enum_field.name,
+                    .description = enum_field.description,
+                    .value = enum_field.value,
+                });
+            }
 
-test "all" {
-    @setEvalBranchQuota(2000);
-    _ = analysis;
-    _ = atdf;
-    _ = gen;
-    _ = svd;
+            return enum_id;
+        },
+    }
 }
 
-test "add_enum_and_apply patch creates enum and applies to fields" {
+test "add_type_and_apply patch creates enum and applies to fields" {
     const allocator = std.testing.allocator;
 
     var db = try Database.create(allocator);
@@ -2219,14 +2320,14 @@ test "add_enum_and_apply patch creates enum and applies to fields" {
         .offset_bits = 0,
     });
 
-    // Apply the add_enum_and_apply patch
-    const patch_zon: [:0]const u8 =
+    // Apply the add_type_and_apply patch
+    const patch_text: [:0]const u8 =
         \\.{
         \\    .{
-        \\        .add_enum_and_apply = .{
+        \\        .add_type_and_apply = .{
         \\            .parent = "types.peripherals.TEST_PERIPHERAL",
-        \\            .@"enum" = .{
-        \\                .name = "TestMode",
+        \\            .type_name = "TestMode",
+        \\            .type = .{ .@"enum" = .{
         \\                .bitsize = 2,
         \\                .fields = .{
         \\                    .{ .value = 0x0, .name = "mode_a" },
@@ -2234,7 +2335,7 @@ test "add_enum_and_apply patch creates enum and applies to fields" {
         \\                    .{ .value = 0x2, .name = "mode_c" },
         \\                    .{ .value = 0x3, .name = "mode_d" },
         \\                },
-        \\            },
+        \\            } },
         \\            .apply_to = .{
         \\                "types.peripherals.TEST_PERIPHERAL.REG0.MODE",
         \\                "types.peripherals.TEST_PERIPHERAL.REG1.MODE",
@@ -2248,7 +2349,11 @@ test "add_enum_and_apply patch creates enum and applies to fields" {
     var diags: std.zon.parse.Diagnostics = .{};
     defer diags.deinit(allocator);
 
-    try db.apply_patch(patch_zon, &diags);
+    const patches = try std.zon.parse.fromSlice([]const Patch, allocator, patch_text, &diags, .{});
+    defer std.zon.parse.free(allocator, patches);
+
+    for (patches) |patch|
+        try db.apply_patch(patch);
 
     // Verify the enum was created
     var arena = std.heap.ArenaAllocator.init(allocator);
@@ -2273,7 +2378,7 @@ test "add_enum_and_apply patch creates enum and applies to fields" {
     try std.testing.expectEqual(enum_info.id, fields2[0].enum_id.?);
 }
 
-test "add_enum_and_apply patch with empty apply_to list" {
+test "add_type_and_apply patch with empty apply_to list" {
     const allocator = std.testing.allocator;
 
     var db = try Database.create(allocator);
@@ -2286,19 +2391,19 @@ test "add_enum_and_apply patch with empty apply_to list" {
     const struct_id = try db.get_peripheral_struct(peripheral_id);
 
     // Apply patch with empty apply_to list (just creates the enum)
-    const patch_zon: [:0]const u8 =
+    const patch_text: [:0]const u8 =
         \\.{
         \\    .{
-        \\        .add_enum_and_apply = .{
+        \\        .add_type_and_apply = .{
         \\            .parent = "types.peripherals.TEST_PERIPHERAL",
-        \\            .@"enum" = .{
-        \\                .name = "UnusedEnum",
+        \\            .type_name = "UnusedEnum",
+        \\            .type = .{ .@"enum" = .{
         \\                .bitsize = 4,
         \\                .fields = .{
         \\                    .{ .value = 0, .name = "value0" },
         \\                    .{ .value = 1, .name = "value1" },
         \\                },
-        \\            },
+        \\            } },
         \\            .apply_to = .{},
         \\        },
         \\    },
@@ -2308,7 +2413,11 @@ test "add_enum_and_apply patch with empty apply_to list" {
     var diags: std.zon.parse.Diagnostics = .{};
     defer diags.deinit(allocator);
 
-    try db.apply_patch(patch_zon, &diags);
+    const patches = try std.zon.parse.fromSlice([]const Patch, allocator, patch_text, &diags, .{});
+    defer std.zon.parse.free(allocator, patches);
+
+    for (patches) |patch|
+        try db.apply_patch(patch);
 
     // Verify the enum was created
     var arena = std.heap.ArenaAllocator.init(allocator);
@@ -2317,7 +2426,7 @@ test "add_enum_and_apply patch with empty apply_to list" {
     try std.testing.expectEqual(@as(u8, 4), enum_info.size_bits);
 }
 
-test "add_enum_and_apply patch with invalid field reference" {
+test "add_type_and_apply patch with invalid field reference" {
     const allocator = std.testing.allocator;
 
     var db = try Database.create(allocator);
@@ -2329,18 +2438,18 @@ test "add_enum_and_apply patch with invalid field reference" {
     });
 
     // Apply patch with invalid field reference
-    const patch_zon: [:0]const u8 =
+    const patch_text: [:0]const u8 =
         \\.{
         \\    .{
-        \\        .add_enum_and_apply = .{
+        \\        .add_type_and_apply = .{
         \\            .parent = "types.peripherals.TEST_PERIPHERAL",
-        \\            .@"enum" = .{
-        \\                .name = "TestEnum",
+        \\            .type_name = "TestEnum",
+        \\            .type = .{ .@"enum" = .{
         \\                .bitsize = 2,
         \\                .fields = .{
         \\                    .{ .value = 0, .name = "value0" },
         \\                },
-        \\            },
+        \\            } },
         \\            .apply_to = .{
         \\                "types.peripherals.TEST_PERIPHERAL.NONEXISTENT.FIELD",
         \\            },
@@ -2352,6 +2461,11 @@ test "add_enum_and_apply patch with invalid field reference" {
     var diags: std.zon.parse.Diagnostics = .{};
     defer diags.deinit(allocator);
 
-    const result = db.apply_patch(patch_zon, &diags);
-    try std.testing.expectError(error.MissingEntity, result);
+    const patches = try std.zon.parse.fromSlice([]const Patch, allocator, patch_text, &diags, .{});
+    defer std.zon.parse.free(allocator, patches);
+
+    for (patches) |patch| {
+        const result = db.apply_patch(patch);
+        try std.testing.expectError(error.MissingEntity, result);
+    }
 }
diff --git a/tools/regz/src/SQL_Options.zig b/tools/regz/src/SQL_Options.zig
deleted file mode 100644
index 76739c6dc..000000000
--- a/tools/regz/src/SQL_Options.zig
+++ /dev/null
@@ -1,34 +0,0 @@
-primary_key: ?PrimaryKey = null,
-foreign_keys: []const ForeignKey = &.{},
-unique_constraints: []const Unique = &.{},
-
-pub const Unique = []const []const u8;
-
-pub const PrimaryKey = struct {
-    name: []const u8,
-    autoincrement: bool = false,
-};
-
-pub const On = enum {
-    no_action,
-    restrict,
-    cascade,
-    set_null,
-    set_default,
-
-    pub fn to_string(on: On) []const u8 {
-        return switch (on) {
-            .no_action => "NO ACTION",
-            .restrict => "RESTRICT",
-            .cascade => "CASCADE",
-            .set_null => "SET NULL",
-            .set_default => "SET DEFAULT",
-        };
-    }
-};
-
-pub const ForeignKey = struct {
-    name: []const u8,
-    on_delete: On = .no_action,
-    on_update: On = .no_action,
-};
diff --git a/tools/regz/src/VirtualFilesystem.zig b/tools/regz/src/VirtualFilesystem.zig
index 4481f0251..2a1c4009e 100644
--- a/tools/regz/src/VirtualFilesystem.zig
+++ b/tools/regz/src/VirtualFilesystem.zig
@@ -13,7 +13,7 @@ const Allocator = std.mem.Allocator;
 const Map = std.AutoArrayHashMapUnmanaged;
 const assert = std.debug.assert;
 
-const Directory = @import("Database.zig").Directory;
+const Directory = @import("Directory.zig");
 
 pub const Kind = enum {
     file,
diff --git a/tools/regz/src/analysis.zig b/tools/regz/src/analysis.zig
index 2ac9e9c74..d940d738f 100644
--- a/tools/regz/src/analysis.zig
+++ b/tools/regz/src/analysis.zig
@@ -2,17 +2,13 @@
 //!
 //! This module provides analysis capabilities to identify and group anonymous
 //! enums that are equivalent (same fields, descriptions, and size) within a
-//! peripheral type. This enables suggesting `add_enum_and_apply` patches.
+//! peripheral type. This enables suggesting `add_type_and_apply` patches.
 const Analysis = @This();
 
 const std = @import("std");
 const Allocator = std.mem.Allocator;
 const Database = @import("Database.zig");
 
-const zqlite = @import("zqlite");
-
-const log = std.log.scoped(.analysis);
-
 db: *Database,
 
 pub const EnumSignature = struct {
diff --git a/tools/regz/src/arch/arm.zig b/tools/regz/src/arch/arm.zig
index 0ff80191d..ad9bd8ee0 100644
--- a/tools/regz/src/arch/arm.zig
+++ b/tools/regz/src/arch/arm.zig
@@ -10,7 +10,7 @@ const DeviceID = Database.DeviceID;
 const gen = @import("../gen.zig");
 const Interrupt = @import("Interrupt.zig");
 
-const svd = @import("../svd.zig");
+const parse_bool = @import("../format/svd.zig").parse_bool;
 
 const log = std.log.scoped(.@"gen.arm");
 
@@ -75,7 +75,7 @@ pub fn load_system_interrupts(db: *Database, device_id: DeviceID, arch: Arch) !v
     const vendor_systick_config = if (try db.get_device_property(db.gpa, device_id, "cpu.vendorSystickConfig")) |str| blk: {
         defer db.gpa.free(str);
 
-        break :blk try svd.parse_bool(str);
+        break :blk try parse_bool(str);
     } else false;
 
     if (!vendor_systick_config) {
diff --git a/tools/regz/src/atdf.zig b/tools/regz/src/format/atdf.zig
similarity index 98%
rename from tools/regz/src/atdf.zig
rename to tools/regz/src/format/atdf.zig
index 70c140570..b46c1ed1c 100644
--- a/tools/regz/src/atdf.zig
+++ b/tools/regz/src/format/atdf.zig
@@ -1,9 +1,8 @@
 const std = @import("std");
-const ArenaAllocator = std.heap.ArenaAllocator;
 const Allocator = std.mem.Allocator;
 const assert = std.debug.assert;
 
-const Database = @import("Database.zig");
+const Database = @import("../Database.zig");
 const DevicePeripheralID = Database.DevicePeripheralID;
 const PeripheralID = Database.PeripheralID;
 const EnumID = Database.EnumID;
@@ -11,8 +10,8 @@ const DeviceID = Database.DeviceID;
 const StructID = Database.StructID;
 const RegisterID = Database.RegisterID;
 
-const xml = @import("xml.zig");
-const Arch = @import("arch.zig").Arch;
+const xml = @import("../xml.zig");
+const Arch = @import("../arch.zig").Arch;
 
 const log = std.log.scoped(.atdf);
 
@@ -602,9 +601,9 @@ fn load_register(
         else
             null,
         .access = if (node.get_attribute("rw")) |access_str|
-            try access_from_string(access_str)
+            Database.Access.try_parse_short(access_str) orelse return error.InvalidAccessStr
         else
-            .read_write,
+            .default,
     });
 
     if (node.get_attribute("modes")) |modes| {
@@ -673,7 +672,7 @@ fn load_field(ctx: *Context, node: xml.Node, peripheral_struct_id: StructID, par
 
                 // FIXME: field specific r/w
                 //if (node.get_attribute("rw")) |access_str| blk: {
-                //    const access = access_from_string(access_str) catch break :blk;
+                //    const access = .try_parse_short(access_str) catch break :blk;
                 //    switch (access) {
                 //        .read_only, .write_only => try db.attrs.access.put(
                 //            db.gpa,
@@ -715,7 +714,7 @@ fn load_field(ctx: *Context, node: xml.Node, peripheral_struct_id: StructID, par
 
         // FIXME: field based access
         //if (node.get_attribute("rw")) |access_str| blk: {
-        //    const access = access_from_string(access_str) catch break :blk;
+        //    const access = .try_parse_short(access_str) catch break :blk;
         //    switch (access) {
         //        .read_only, .write_only => try db.attrs.access.put(
         //            db.gpa,
@@ -760,17 +759,6 @@ fn load_field(ctx: *Context, node: xml.Node, peripheral_struct_id: StructID, par
     }
 }
 
-fn access_from_string(str: []const u8) !Database.Access {
-    return if (std.mem.eql(u8, "RW", str))
-        .read_write
-    else if (std.mem.eql(u8, "R", str))
-        .read_only
-    else if (std.mem.eql(u8, "W", str))
-        .write_only
-    else
-        error.InvalidAccessStr;
-}
-
 fn load_enum(
     ctx: *Context,
     module_node: xml.Node,
@@ -1094,7 +1082,6 @@ fn validate_attrs(node: xml.Node, attrs: []const []const u8) void {
     }
 }
 
-const expect = std.testing.expect;
 const expectEqual = std.testing.expectEqual;
 const expectEqualStrings = std.testing.expectEqualStrings;
 
diff --git a/tools/regz/src/embassy.zig b/tools/regz/src/format/embassy.zig
similarity index 99%
rename from tools/regz/src/embassy.zig
rename to tools/regz/src/format/embassy.zig
index 7b8234816..8823de06a 100644
--- a/tools/regz/src/embassy.zig
+++ b/tools/regz/src/format/embassy.zig
@@ -1,3 +1,8 @@
+const std = @import("std");
+const Database = @import("../Database.zig");
+const Arch = @import("../arch.zig").Arch;
+const arm = @import("../arch/arm.zig");
+
 pub const core_to_cpu = std.StaticStringMap([]const u8).initComptime(&.{
     .{ "cm0", "cortex_m0" },
     .{ "cm0p", "cortex_m0plus" },
@@ -598,9 +603,3 @@ fn get_section(child_full_name: []const u8) []const u8 {
     }
     @panic("Unhandled extends Type");
 }
-
-const std = @import("std");
-const Database = @import("Database.zig");
-const Arch = @import("arch.zig").Arch;
-const arm = @import("arch/arm.zig");
-const FS_Directory = @import("FS_Directory.zig");
diff --git a/tools/regz/src/svd.zig b/tools/regz/src/format/svd.zig
similarity index 97%
rename from tools/regz/src/svd.zig
rename to tools/regz/src/format/svd.zig
index 050b691f0..4de330980 100644
--- a/tools/regz/src/svd.zig
+++ b/tools/regz/src/format/svd.zig
@@ -1,16 +1,14 @@
 const std = @import("std");
 const ArenaAllocator = std.heap.ArenaAllocator;
 const Allocator = std.mem.Allocator;
-const assert = std.debug.assert;
 
-const xml = @import("xml.zig");
-const Arch = @import("arch.zig").Arch;
+const xml = @import("../xml.zig");
+const Arch = @import("../arch.zig").Arch;
 
-const Database = @import("Database.zig");
+const Database = @import("../Database.zig");
 const Access = Database.Access;
 const StructID = Database.StructID;
 const DeviceID = Database.DeviceID;
-const PeripheralID = Database.PeripheralID;
 const RegisterID = Database.RegisterID;
 const EnumID = Database.EnumID;
 
@@ -481,7 +479,7 @@ fn load_register_with_dim_element_group(ctx: *Context, node: xml.Node, parent: S
             },
             .size_bits = size,
             .count = if (dim_elements.resolve() == .array) dim_elements.dim else null,
-            .access = register_props.access orelse .read_write,
+            .access = register_props.access orelse .default,
             .reset_mask = register_props.reset_mask,
             .reset_value = register_props.reset_value,
         });
@@ -514,7 +512,7 @@ fn load_single_register(ctx: *Context, node: xml.Node, parent: StructID) !void {
             return error.MissingRegisterOffset,
         .size_bits = size,
         .count = null,
-        .access = register_props.access orelse .read_write,
+        .access = register_props.access orelse .default,
         .reset_mask = register_props.reset_mask,
         .reset_value = register_props.reset_value,
     });
@@ -550,10 +548,7 @@ fn load_field(ctx: *Context, node: xml.Node, register_id: RegisterID, props: *co
         null;
 
     const access = if (node.get_value("access")) |access_str|
-        parse_access(access_str) catch blk: {
-            log.warn("Failed to parse access string '{s}', it must be one of 'read-value', 'write-only', 'read-write', 'writeOnce', or 'read-writeOnce', defaulting to 'read-write'", .{access_str});
-            break :blk .read_write;
-        }
+        Access.parse(access_str)
     else
         props.access;
 
@@ -680,11 +675,6 @@ pub const DimableIdentifier = struct {
 /// pattern: [0-9]+\-[0-9]+|[A-Z]-[A-Z]|[_0-9a-zA-Z]+(,\s*[_0-9a-zA-Z]+)+
 pub const DimIndex = struct {};
 
-const DimType = enum {
-    array,
-    list,
-};
-
 const expect = std.testing.expect;
 const expectEqual = std.testing.expectEqual;
 const expectError = std.testing.expectError;
@@ -978,12 +968,7 @@ const RegisterProperties = struct {
             else
                 null,
             .access = if (node.get_value("access")) |access_str|
-                parse_access(access_str) catch blk: {
-                    log.warn("Failed to parse access string '{s}', it must be one of 'read-only'," ++
-                        "'write-only', 'write', 'read-write', 'writeOnce', or 'read-writeOnce', " ++
-                        "defaulting to 'read-write'", .{access_str});
-                    break :blk .read_write;
-                }
+                Access.parse(access_str)
             else
                 null,
             .protection = null,
@@ -999,25 +984,6 @@ const RegisterProperties = struct {
     }
 };
 
-fn parse_access(str: []const u8) !Access {
-    return if (std.ascii.eqlIgnoreCase("read-only", str))
-        Access.read_only
-    else if (std.ascii.eqlIgnoreCase("write-only", str))
-        Access.write_only
-    else if (std.ascii.eqlIgnoreCase("write", str))
-        Access.write_only
-    else if (std.ascii.eqlIgnoreCase("read-write", str))
-        Access.read_write
-    else if (std.ascii.eqlIgnoreCase("writeOnce", str))
-        Access.write_once
-    else if (std.ascii.eqlIgnoreCase("read-writeOnce", str))
-        Access.read_write_once
-    else blk: {
-        log.warn("invalid access type: '{s}'", .{str});
-        break :blk error.UnknownAccessType;
-    };
-}
-
 test "svd.device register properties" {
     const text =
         \\<device>
diff --git a/tools/regz/src/targetdb.zig b/tools/regz/src/format/targetdb.zig
similarity index 95%
rename from tools/regz/src/targetdb.zig
rename to tools/regz/src/format/targetdb.zig
index ade6d1796..c01eab5fb 100644
--- a/tools/regz/src/targetdb.zig
+++ b/tools/regz/src/format/targetdb.zig
@@ -1,13 +1,13 @@
 const std = @import("std");
-const xml = @import("xml.zig");
+const xml = @import("../xml.zig");
 
-const Database = @import("Database.zig");
+const Database = @import("../Database.zig");
 const DeviceID = Database.DeviceID;
 const PeripheralID = Database.PeripheralID;
 const RegisterID = Database.RegisterID;
 const StructID = Database.StructID;
 const EnumID = Database.EnumID;
-const Arch = @import("arch.zig").Arch;
+const Arch = @import("../arch.zig").Arch;
 
 const log = std.log.scoped(.target_db);
 
@@ -277,21 +277,7 @@ fn load_bitfield(db: *Database, register_id: RegisterID, node: xml.Node) !void {
     const end_bit = try std.fmt.parseInt(u8, end_str, 0);
 
     const access_str = node.get_attribute("rwaccess");
-    const access: Database.Access = if (access_str) |str|
-        if (std.mem.eql(u8, str, "RW"))
-            .read_write
-        else if (std.mem.eql(u8, str, "R/W"))
-            .read_write
-        else if (std.mem.eql(u8, str, "R"))
-            .read_only
-        else if (std.mem.eql(u8, str, "W"))
-            .write_only
-        else blk: {
-            log.info("unrecognized access string: '{s}'", .{str});
-            break :blk .read_write;
-        }
-    else
-        .read_write;
+    const access: Database.Access = if (access_str) |str| .parse_short(str) else .default;
 
     const enum_id: ?EnumID = if (node.find_child(&.{"bitenum"}) != null) blk: {
         const enum_id = try db.create_enum(null, .{
diff --git a/tools/regz/src/gen.zig b/tools/regz/src/gen.zig
index c5bff78d1..7f11cc369 100644
--- a/tools/regz/src/gen.zig
+++ b/tools/regz/src/gen.zig
@@ -1147,24 +1147,26 @@ fn write_register(
             register.size_bits,
         });
 
-        try write_fields(db, arena, fields, register.size_bits, register_reset, writer);
+        try write_fields_and_access(db, arena, fields, register.size_bits, register_reset, writer);
         try writer.writeAll("}),\n");
     } else if (array_prefix.len != 0) {
-        try writer.print("{f}: {s}u{},\n", .{
+        try writer.print("{f}: {s}mmio.Mmio(u{}, .{f}),\n", .{
             std.zig.fmtId(register.name),
             array_prefix,
             register.size_bits,
+            std.zig.fmtId(@tagName(register.access)),
         });
     } else {
-        try writer.print("{f}: u{}", .{
+        try writer.print("{f}: mmio.Mmio(u{}, .{f})", .{
             std.zig.fmtId(register.name),
             register.size_bits,
+            std.zig.fmtId(@tagName(register.access)),
         });
 
         // Just assume non-masked areas are zero I guess
         if (register_reset) |rr| {
             const mask = (@as(u64, 1) << @intCast(register.size_bits)) - 1;
-            try writer.print(" = 0x{X}", .{rr.value & mask});
+            try writer.print(" = .{{ .raw = 0x{X} }}", .{rr.value & mask});
         }
 
         try writer.writeAll(",\n");
@@ -1193,7 +1195,7 @@ fn get_field_default(field: Database.StructField, maybe_register_reset: ?Registe
     return (register_reset.value & field_mask) >> @intCast(field.offset_bits);
 }
 
-fn write_fields(
+fn write_fields_and_access(
     db: *Database,
     arena: Allocator,
     fields: []const Database.StructField,
@@ -1235,6 +1237,17 @@ fn write_fields(
 
     var offset: u64 = 0;
 
+    const RegAndAccess = union(enum) {
+        normal: struct {
+            name: []const u8,
+            access: ?Database.Access,
+        },
+        reserved: u8,
+        padding,
+    };
+
+    var access: std.ArrayList(RegAndAccess) = .empty;
+
     for (expanded_fields.items) |field| {
         log.debug("next field: offset={} field.offset_bits={}", .{ offset, field.offset_bits });
         if (offset > field.offset_bits) {
@@ -1260,6 +1273,7 @@ fn write_fields(
         if (offset < field.offset_bits) {
             try writer.print("reserved{}: u{} = 0,\n", .{ field.offset_bits, field.offset_bits - offset });
             offset = field.offset_bits;
+            try access.append(arena, .{ .reserved = field.offset_bits });
         }
         assert(offset == field.offset_bits);
 
@@ -1330,6 +1344,8 @@ fn write_fields(
 
         log.debug("adding size bits to offset: offset={} field.size_bits={}", .{ offset, field.size_bits });
         offset += field.size_bits;
+
+        try access.append(arena, .{ .normal = .{ .name = field.name, .access = field.access } });
     }
 
     log.debug("before padding: offset={} register_size_bits={}", .{ offset, register_size_bits });
@@ -1337,10 +1353,27 @@ fn write_fields(
     if (offset < register_size_bits) {
         log.debug("writing padding", .{});
         try writer.print("padding: u{} = 0,\n", .{register_size_bits - offset});
+        try access.append(arena, .padding);
     } else {
         log.debug("No padding", .{});
     }
 
+    try writer.writeAll("}, .{\n");
+
+    for (access.items) |it| switch (it) {
+        .normal => |data| {
+            try writer.print(
+                ".{f} = .{f},\n",
+                .{
+                    std.zig.fmtId(data.name),
+                    std.zig.fmtId(@tagName(data.access orelse Database.Access.default)),
+                },
+            );
+        },
+        .reserved => |num| try writer.print(".reserved{} = .reserved,\n", .{num}),
+        .padding => try writer.writeAll(".padding = .reserved,\n"),
+    };
+
     try out_writer.writeAll(buf.written());
 }
 
@@ -1475,7 +1508,7 @@ test "gen.StructFieldIterator.single register" {
         .name = "TEST_REGISTER",
         .size_bits = 32,
         .offset_bytes = 0,
-        .access = .read_write,
+        .access = .default,
         .reset_mask = 0xFF,
         .reset_value = 0xAA,
         .count = null,
@@ -1543,7 +1576,7 @@ test "gen.StructFieldIterator.two registers overlap but one is smaller" {
             .name = "TEST_REGISTER1",
             .size_bits = 32,
             .offset_bytes = 0,
-            .access = .read_write,
+            .access = .default,
             .reset_mask = 0xFF,
             .reset_value = 0xAA,
             .count = null,
@@ -1555,7 +1588,7 @@ test "gen.StructFieldIterator.two registers overlap but one is smaller" {
             .name = "TEST_REGISTER2",
             .size_bits = 16,
             .offset_bytes = 0,
-            .access = .read_write,
+            .access = .default,
             .reset_mask = 0xFF,
             .reset_value = 0xAA,
             .count = null,
@@ -1584,7 +1617,7 @@ test "gen.StructFieldIterator.two registers overlap with different offsets" {
             .name = "TEST_REGISTER1",
             .size_bits = 32,
             .offset_bytes = 0,
-            .access = .read_write,
+            .access = .default,
             .reset_mask = 0xFF,
             .reset_value = 0xAA,
             .count = null,
@@ -1596,7 +1629,7 @@ test "gen.StructFieldIterator.two registers overlap with different offsets" {
             .name = "TEST_REGISTER2",
             .size_bits = 16,
             .offset_bytes = 2,
-            .access = .read_write,
+            .access = .default,
             .reset_mask = 0xFF,
             .reset_value = 0xAA,
             .count = null,
@@ -1647,7 +1680,7 @@ test "gen.StructFieldIterator.one nested struct field and a register" {
         .name = "TEST_REGISTER",
         .size_bits = 32,
         .offset_bytes = 0,
-        .access = .read_write,
+        .access = .default,
         .reset_mask = 0xFF,
         .reset_value = 0xAA,
         .count = null,
@@ -1722,7 +1755,7 @@ test "gen.peripheral instantiation" {
     var vfs: VirtualFilesystem = .init(std.testing.allocator);
     defer vfs.deinit();
 
-    try db.to_zig(vfs.dir(), .{});
+    try to_zig(db, vfs.dir(), .{});
     try expect_output(&.{
         .{
             .path = "TEST_DEVICE.zig",
@@ -1762,17 +1795,11 @@ test "gen.peripheral instantiation" {
         },
         .{
             .path = "types.zig",
-            .content =
-            \\pub const peripherals = @import("types/peripherals.zig");
-            \\
-            ,
+            .content = "pub const peripherals = @import(\"types/peripherals.zig\");\n",
         },
         .{
             .path = "peripherals.zig",
-            .content =
-            \\pub const TEST_PERIPHERAL = @import("peripherals/TEST_PERIPHERAL.zig").TEST_PERIPHERAL;
-            \\
-            ,
+            .content = "pub const TEST_PERIPHERAL = @import(\"peripherals/TEST_PERIPHERAL.zig\").TEST_PERIPHERAL;\n",
         },
         .{
             .path = "peripherals/TEST_PERIPHERAL.zig",
@@ -1787,6 +1814,9 @@ test "gen.peripheral instantiation" {
             \\    TEST_REGISTER: mmio.Mmio(packed struct(u32) {
             \\        TEST_FIELD: u1 = 0x1,
             \\        padding: u31 = 0,
+            \\    }, .{
+            \\        .TEST_FIELD = .read_write,
+            \\        .padding = .reserved,
             \\    }),
             \\};
             \\
@@ -1805,7 +1835,7 @@ test "gen.peripherals with a shared type" {
     var vfs: VirtualFilesystem = .init(std.testing.allocator);
     defer vfs.deinit();
 
-    try db.to_zig(vfs.dir(), .{});
+    try to_zig(db, vfs.dir(), .{});
     try expect_output(&.{
         .{
             .path = "TEST_DEVICE.zig",
@@ -1846,17 +1876,11 @@ test "gen.peripherals with a shared type" {
         },
         .{
             .path = "types.zig",
-            .content =
-            \\pub const peripherals = @import("types/peripherals.zig");
-            \\
-            ,
+            .content = "pub const peripherals = @import(\"types/peripherals.zig\");\n",
         },
         .{
             .path = "peripherals.zig",
-            .content =
-            \\pub const TEST_PERIPHERAL = @import("peripherals/TEST_PERIPHERAL.zig").TEST_PERIPHERAL;
-            \\
-            ,
+            .content = "pub const TEST_PERIPHERAL = @import(\"peripherals/TEST_PERIPHERAL.zig\").TEST_PERIPHERAL;\n",
         },
         .{
             .path = "peripherals/TEST_PERIPHERAL.zig",
@@ -1871,6 +1895,9 @@ test "gen.peripherals with a shared type" {
             \\    TEST_REGISTER: mmio.Mmio(packed struct(u32) {
             \\        TEST_FIELD: u1,
             \\        padding: u31 = 0,
+            \\    }, .{
+            \\        .TEST_FIELD = .read_write,
+            \\        .padding = .reserved,
             \\    }),
             \\};
             \\
@@ -1889,21 +1916,15 @@ test "gen.peripheral with modes" {
     var vfs: VirtualFilesystem = .init(std.testing.allocator);
     defer vfs.deinit();
 
-    try db.to_zig(vfs.dir(), .{});
+    try to_zig(db, vfs.dir(), .{});
     try expect_output(&.{
         .{
             .path = "types.zig",
-            .content =
-            \\pub const peripherals = @import("types/peripherals.zig");
-            \\
-            ,
+            .content = "pub const peripherals = @import(\"types/peripherals.zig\");\n",
         },
         .{
             .path = "peripherals.zig",
-            .content =
-            \\pub const TEST_PERIPHERAL = @import("peripherals/TEST_PERIPHERAL.zig").TEST_PERIPHERAL;
-            \\
-            ,
+            .content = "pub const TEST_PERIPHERAL = @import(\"peripherals/TEST_PERIPHERAL.zig\").TEST_PERIPHERAL;\n",
         },
         .{
             .path = "peripherals/TEST_PERIPHERAL.zig",
@@ -1942,20 +1963,26 @@ test "gen.peripheral with modes" {
             \\
             \\    TEST_MODE1: extern struct {
             \\        /// offset: 0x00
-            \\        TEST_REGISTER1: u32,
+            \\        TEST_REGISTER1: mmio.Mmio(u32, .read_write),
             \\        /// offset: 0x04
             \\        COMMON_REGISTER: mmio.Mmio(packed struct(u32) {
             \\            TEST_FIELD: u1,
             \\            padding: u31 = 0,
+            \\        }, .{
+            \\            .TEST_FIELD = .read_write,
+            \\            .padding = .reserved,
             \\        }),
             \\    },
             \\    TEST_MODE2: extern struct {
             \\        /// offset: 0x00
-            \\        TEST_REGISTER2: u32,
+            \\        TEST_REGISTER2: mmio.Mmio(u32, .read_write),
             \\        /// offset: 0x04
             \\        COMMON_REGISTER: mmio.Mmio(packed struct(u32) {
             \\            TEST_FIELD: u1,
             \\            padding: u31 = 0,
+            \\        }, .{
+            \\            .TEST_FIELD = .read_write,
+            \\            .padding = .reserved,
             \\        }),
             \\    },
             \\};
@@ -1975,21 +2002,15 @@ test "gen.peripheral with enum" {
     var vfs: VirtualFilesystem = .init(std.testing.allocator);
     defer vfs.deinit();
 
-    try db.to_zig(vfs.dir(), .{});
+    try to_zig(db, vfs.dir(), .{});
     try expect_output(&.{
         .{
             .path = "types.zig",
-            .content =
-            \\pub const peripherals = @import("types/peripherals.zig");
-            \\
-            ,
+            .content = "pub const peripherals = @import(\"types/peripherals.zig\");\n",
         },
         .{
             .path = "peripherals.zig",
-            .content =
-            \\pub const TEST_PERIPHERAL = @import("peripherals/TEST_PERIPHERAL.zig").TEST_PERIPHERAL;
-            \\
-            ,
+            .content = "pub const TEST_PERIPHERAL = @import(\"peripherals/TEST_PERIPHERAL.zig\").TEST_PERIPHERAL;\n",
         },
         .{
             .path = "peripherals/TEST_PERIPHERAL.zig",
@@ -2007,7 +2028,7 @@ test "gen.peripheral with enum" {
             \\    };
             \\
             \\    /// offset: 0x00
-            \\    TEST_REGISTER: u8,
+            \\    TEST_REGISTER: mmio.Mmio(u8, .read_write),
             \\};
             \\
             ,
@@ -2025,21 +2046,15 @@ test "gen.peripheral with enum, enum is exhausted of values" {
     var vfs: VirtualFilesystem = .init(std.testing.allocator);
     defer vfs.deinit();
 
-    try db.to_zig(vfs.dir(), .{});
+    try to_zig(db, vfs.dir(), .{});
     try expect_output(&.{
         .{
             .path = "types.zig",
-            .content =
-            \\pub const peripherals = @import("types/peripherals.zig");
-            \\
-            ,
+            .content = "pub const peripherals = @import(\"types/peripherals.zig\");\n",
         },
         .{
             .path = "peripherals.zig",
-            .content =
-            \\pub const TEST_PERIPHERAL = @import("peripherals/TEST_PERIPHERAL.zig").TEST_PERIPHERAL;
-            \\
-            ,
+            .content = "pub const TEST_PERIPHERAL = @import(\"peripherals/TEST_PERIPHERAL.zig\").TEST_PERIPHERAL;\n",
         },
         .{
             .path = "peripherals/TEST_PERIPHERAL.zig",
@@ -2056,7 +2071,7 @@ test "gen.peripheral with enum, enum is exhausted of values" {
             \\    };
             \\
             \\    /// offset: 0x00
-            \\    TEST_REGISTER: u8,
+            \\    TEST_REGISTER: mmio.Mmio(u8, .read_write),
             \\};
             \\
             ,
@@ -2074,21 +2089,15 @@ test "gen.field with named enum" {
     var vfs: VirtualFilesystem = .init(std.testing.allocator);
     defer vfs.deinit();
 
-    try db.to_zig(vfs.dir(), .{});
+    try to_zig(db, vfs.dir(), .{});
     try expect_output(&.{
         .{
             .path = "types.zig",
-            .content =
-            \\pub const peripherals = @import("types/peripherals.zig");
-            \\
-            ,
+            .content = "pub const peripherals = @import(\"types/peripherals.zig\");\n",
         },
         .{
             .path = "peripherals.zig",
-            .content =
-            \\pub const TEST_PERIPHERAL = @import("peripherals/TEST_PERIPHERAL.zig").TEST_PERIPHERAL;
-            \\
-            ,
+            .content = "pub const TEST_PERIPHERAL = @import(\"peripherals/TEST_PERIPHERAL.zig\").TEST_PERIPHERAL;\n",
         },
         .{
             .path = "peripherals/TEST_PERIPHERAL.zig",
@@ -2109,6 +2118,9 @@ test "gen.field with named enum" {
             \\    TEST_REGISTER: mmio.Mmio(packed struct(u8) {
             \\        TEST_FIELD: TEST_ENUM,
             \\        padding: u4 = 0,
+            \\    }, .{
+            \\        .TEST_FIELD = .read_write,
+            \\        .padding = .reserved,
             \\    }),
             \\};
             \\
@@ -2127,21 +2139,15 @@ test "gen.field with named enum and named default" {
     var vfs: VirtualFilesystem = .init(std.testing.allocator);
     defer vfs.deinit();
 
-    try db.to_zig(vfs.dir(), .{});
+    try to_zig(db, vfs.dir(), .{});
     try expect_output(&.{
         .{
             .path = "types.zig",
-            .content =
-            \\pub const peripherals = @import("types/peripherals.zig");
-            \\
-            ,
+            .content = "pub const peripherals = @import(\"types/peripherals.zig\");\n",
         },
         .{
             .path = "peripherals.zig",
-            .content =
-            \\pub const TEST_PERIPHERAL = @import("peripherals/TEST_PERIPHERAL.zig").TEST_PERIPHERAL;
-            \\
-            ,
+            .content = "pub const TEST_PERIPHERAL = @import(\"peripherals/TEST_PERIPHERAL.zig\").TEST_PERIPHERAL;\n",
         },
         .{
             .path = "peripherals/TEST_PERIPHERAL.zig",
@@ -2162,6 +2168,9 @@ test "gen.field with named enum and named default" {
             \\    TEST_REGISTER: mmio.Mmio(packed struct(u8) {
             \\        TEST_FIELD: TEST_ENUM = .TEST_ENUM_FIELD2,
             \\        padding: u4 = 0,
+            \\    }, .{
+            \\        .TEST_FIELD = .read_write,
+            \\        .padding = .reserved,
             \\    }),
             \\};
             \\
@@ -2180,21 +2189,15 @@ test "gen.field with named enum and unnamed default" {
     var vfs: VirtualFilesystem = .init(std.testing.allocator);
     defer vfs.deinit();
 
-    try db.to_zig(vfs.dir(), .{});
+    try to_zig(db, vfs.dir(), .{});
     try expect_output(&.{
         .{
             .path = "types.zig",
-            .content =
-            \\pub const peripherals = @import("types/peripherals.zig");
-            \\
-            ,
+            .content = "pub const peripherals = @import(\"types/peripherals.zig\");\n",
         },
         .{
             .path = "peripherals.zig",
-            .content =
-            \\pub const TEST_PERIPHERAL = @import("peripherals/TEST_PERIPHERAL.zig").TEST_PERIPHERAL;
-            \\
-            ,
+            .content = "pub const TEST_PERIPHERAL = @import(\"peripherals/TEST_PERIPHERAL.zig\").TEST_PERIPHERAL;\n",
         },
         .{
             .path = "peripherals/TEST_PERIPHERAL.zig",
@@ -2215,6 +2218,9 @@ test "gen.field with named enum and unnamed default" {
             \\    TEST_REGISTER: mmio.Mmio(packed struct(u8) {
             \\        TEST_FIELD: TEST_ENUM = @enumFromInt(0xA),
             \\        padding: u4 = 0,
+            \\    }, .{
+            \\        .TEST_FIELD = .read_write,
+            \\        .padding = .reserved,
             \\    }),
             \\};
             \\
@@ -2233,21 +2239,15 @@ test "gen.field with anonymous enum" {
     var vfs: VirtualFilesystem = .init(std.testing.allocator);
     defer vfs.deinit();
 
-    try db.to_zig(vfs.dir(), .{});
+    try to_zig(db, vfs.dir(), .{});
     try expect_output(&.{
         .{
             .path = "types.zig",
-            .content =
-            \\pub const peripherals = @import("types/peripherals.zig");
-            \\
-            ,
+            .content = "pub const peripherals = @import(\"types/peripherals.zig\");\n",
         },
         .{
             .path = "peripherals.zig",
-            .content =
-            \\pub const TEST_PERIPHERAL = @import("peripherals/TEST_PERIPHERAL.zig").TEST_PERIPHERAL;
-            \\
-            ,
+            .content = "pub const TEST_PERIPHERAL = @import(\"peripherals/TEST_PERIPHERAL.zig\").TEST_PERIPHERAL;\n",
         },
         .{
             .path = "peripherals/TEST_PERIPHERAL.zig",
@@ -2266,6 +2266,9 @@ test "gen.field with anonymous enum" {
             \\            _,
             \\        },
             \\        padding: u4 = 0,
+            \\    }, .{
+            \\        .TEST_FIELD = .read_write,
+            \\        .padding = .reserved,
             \\    }),
             \\};
             \\
@@ -2284,21 +2287,15 @@ test "gen.field with anonymous enum and default" {
     var vfs: VirtualFilesystem = .init(std.testing.allocator);
     defer vfs.deinit();
 
-    try db.to_zig(vfs.dir(), .{});
+    try to_zig(db, vfs.dir(), .{});
     try expect_output(&.{
         .{
             .path = "types.zig",
-            .content =
-            \\pub const peripherals = @import("types/peripherals.zig");
-            \\
-            ,
+            .content = "pub const peripherals = @import(\"types/peripherals.zig\");\n",
         },
         .{
             .path = "peripherals.zig",
-            .content =
-            \\pub const TEST_PERIPHERAL = @import("peripherals/TEST_PERIPHERAL.zig").TEST_PERIPHERAL;
-            \\
-            ,
+            .content = "pub const TEST_PERIPHERAL = @import(\"peripherals/TEST_PERIPHERAL.zig\").TEST_PERIPHERAL;\n",
         },
         .{
             .path = "peripherals/TEST_PERIPHERAL.zig",
@@ -2317,6 +2314,9 @@ test "gen.field with anonymous enum and default" {
             \\            _,
             \\        } = .TEST_ENUM_FIELD2,
             \\        padding: u4 = 0,
+            \\    }, .{
+            \\        .TEST_FIELD = .read_write,
+            \\        .padding = .reserved,
             \\    }),
             \\};
             \\
@@ -2335,7 +2335,7 @@ test "gen.namespaced register groups" {
     var vfs: VirtualFilesystem = .init(std.testing.allocator);
     defer vfs.deinit();
 
-    try db.to_zig(vfs.dir(), .{});
+    try to_zig(db, vfs.dir(), .{});
     try expect_output(&.{
         .{
             .path = "ATmega328P.zig",
@@ -2376,17 +2376,11 @@ test "gen.namespaced register groups" {
         },
         .{
             .path = "types.zig",
-            .content =
-            \\pub const peripherals = @import("types/peripherals.zig");
-            \\
-            ,
+            .content = "pub const peripherals = @import(\"types/peripherals.zig\");\n",
         },
         .{
             .path = "peripherals.zig",
-            .content =
-            \\pub const PORT = @import("peripherals/PORT.zig");
-            \\
-            ,
+            .content = "pub const PORT = @import(\"peripherals/PORT.zig\");\n",
         },
         .{
             .path = "peripherals/PORT.zig",
@@ -2398,20 +2392,20 @@ test "gen.namespaced register groups" {
             \\
             \\pub const PORTB = extern struct {
             \\    /// offset: 0x00
-            \\    PORTB: u8,
+            \\    PORTB: mmio.Mmio(u8, .read_write),
             \\    /// offset: 0x01
-            \\    DDRB: u8,
+            \\    DDRB: mmio.Mmio(u8, .read_write),
             \\    /// offset: 0x02
-            \\    PINB: u8,
+            \\    PINB: mmio.Mmio(u8, .read_write),
             \\};
             \\
             \\pub const PORTC = extern struct {
             \\    /// offset: 0x00
-            \\    PORTC: u8,
+            \\    PORTC: mmio.Mmio(u8, .read_write),
             \\    /// offset: 0x01
-            \\    DDRC: u8,
+            \\    DDRC: mmio.Mmio(u8, .read_write),
             \\    /// offset: 0x02
-            \\    PINC: u8,
+            \\    PINC: mmio.Mmio(u8, .read_write),
             \\};
             \\
             ,
@@ -2429,7 +2423,7 @@ test "gen.peripheral with reserved register" {
     var vfs: VirtualFilesystem = .init(std.testing.allocator);
     defer vfs.deinit();
 
-    try db.to_zig(vfs.dir(), .{});
+    try to_zig(db, vfs.dir(), .{});
     try expect_output(&.{
         .{
             .path = "ATmega328P.zig",
@@ -2469,17 +2463,11 @@ test "gen.peripheral with reserved register" {
         },
         .{
             .path = "types.zig",
-            .content =
-            \\pub const peripherals = @import("types/peripherals.zig");
-            \\
-            ,
+            .content = "pub const peripherals = @import(\"types/peripherals.zig\");\n",
         },
         .{
             .path = "peripherals.zig",
-            .content =
-            \\pub const PORTB = @import("peripherals/PORTB.zig").PORTB;
-            \\
-            ,
+            .content = "pub const PORTB = @import(\"peripherals/PORTB.zig\").PORTB;\n",
         },
         .{
             .path = "peripherals/PORTB.zig",
@@ -2491,11 +2479,11 @@ test "gen.peripheral with reserved register" {
             \\
             \\pub const PORTB = extern struct {
             \\    /// offset: 0x00
-            \\    PORTB: u32,
+            \\    PORTB: mmio.Mmio(u32, .read_write),
             \\    /// offset: 0x04
             \\    reserved4: [4]u8,
             \\    /// offset: 0x08
-            \\    PINB: u32,
+            \\    PINB: mmio.Mmio(u32, .read_write),
             \\};
             \\
             ,
@@ -2513,7 +2501,7 @@ test "gen.peripheral with count" {
     var vfs: VirtualFilesystem = .init(std.testing.allocator);
     defer vfs.deinit();
 
-    try db.to_zig(vfs.dir(), .{});
+    try to_zig(db, vfs.dir(), .{});
     try expect_output(&.{
         .{
             .path = "ATmega328P.zig",
@@ -2553,17 +2541,11 @@ test "gen.peripheral with count" {
         },
         .{
             .path = "types.zig",
-            .content =
-            \\pub const peripherals = @import("types/peripherals.zig");
-            \\
-            ,
+            .content = "pub const peripherals = @import(\"types/peripherals.zig\");\n",
         },
         .{
             .path = "peripherals.zig",
-            .content =
-            \\pub const PORTB = @import("peripherals/PORTB.zig").PORTB;
-            \\
-            ,
+            .content = "pub const PORTB = @import(\"peripherals/PORTB.zig\").PORTB;\n",
         },
         .{
             .path = "peripherals/PORTB.zig",
@@ -2575,11 +2557,11 @@ test "gen.peripheral with count" {
             \\
             \\pub const PORTB = extern struct {
             \\    /// offset: 0x00
-            \\    PORTB: u8,
+            \\    PORTB: mmio.Mmio(u8, .read_write),
             \\    /// offset: 0x01
-            \\    DDRB: u8,
+            \\    DDRB: mmio.Mmio(u8, .read_write),
             \\    /// offset: 0x02
-            \\    PINB: u8,
+            \\    PINB: mmio.Mmio(u8, .read_write),
             \\};
             \\
             ,
@@ -2597,7 +2579,7 @@ test "gen.peripheral with count, padding required" {
     var vfs: VirtualFilesystem = .init(std.testing.allocator);
     defer vfs.deinit();
 
-    try db.to_zig(vfs.dir(), .{});
+    try to_zig(db, vfs.dir(), .{});
     try expect_output(&.{
         .{
             .path = "ATmega328P.zig",
@@ -2637,17 +2619,11 @@ test "gen.peripheral with count, padding required" {
         },
         .{
             .path = "types.zig",
-            .content =
-            \\pub const peripherals = @import("types/peripherals.zig");
-            \\
-            ,
+            .content = "pub const peripherals = @import(\"types/peripherals.zig\");\n",
         },
         .{
             .path = "peripherals.zig",
-            .content =
-            \\pub const PORTB = @import("peripherals/PORTB.zig").PORTB;
-            \\
-            ,
+            .content = "pub const PORTB = @import(\"peripherals/PORTB.zig\").PORTB;\n",
         },
         .{
             .path = "peripherals/PORTB.zig",
@@ -2659,11 +2635,11 @@ test "gen.peripheral with count, padding required" {
             \\
             \\pub const PORTB = extern struct {
             \\    /// offset: 0x00
-            \\    PORTB: u8,
+            \\    PORTB: mmio.Mmio(u8, .read_write),
             \\    /// offset: 0x01
-            \\    DDRB: u8,
+            \\    DDRB: mmio.Mmio(u8, .read_write),
             \\    /// offset: 0x02
-            \\    PINB: u8,
+            \\    PINB: mmio.Mmio(u8, .read_write),
             \\    padding: [1]u8,
             \\};
             \\
@@ -2682,7 +2658,7 @@ test "gen.register with count" {
     var vfs: VirtualFilesystem = .init(std.testing.allocator);
     defer vfs.deinit();
 
-    try db.to_zig(vfs.dir(), .{});
+    try to_zig(db, vfs.dir(), .{});
     try expect_output(&.{
         .{
             .path = "ATmega328P.zig",
@@ -2722,17 +2698,11 @@ test "gen.register with count" {
         },
         .{
             .path = "types.zig",
-            .content =
-            \\pub const peripherals = @import("types/peripherals.zig");
-            \\
-            ,
+            .content = "pub const peripherals = @import(\"types/peripherals.zig\");\n",
         },
         .{
             .path = "peripherals.zig",
-            .content =
-            \\pub const PORTB = @import("peripherals/PORTB.zig").PORTB;
-            \\
-            ,
+            .content = "pub const PORTB = @import(\"peripherals/PORTB.zig\").PORTB;\n",
         },
         .{
             .path = "peripherals/PORTB.zig",
@@ -2744,11 +2714,11 @@ test "gen.register with count" {
             \\
             \\pub const PORTB = extern struct {
             \\    /// offset: 0x00
-            \\    PORTB: [4]u8,
+            \\    PORTB: [4]mmio.Mmio(u8, .read_write),
             \\    /// offset: 0x04
-            \\    DDRB: u8,
+            \\    DDRB: mmio.Mmio(u8, .read_write),
             \\    /// offset: 0x05
-            \\    PINB: u8,
+            \\    PINB: mmio.Mmio(u8, .read_write),
             \\};
             \\
             ,
@@ -2766,7 +2736,7 @@ test "gen.register with count and fields" {
     var vfs: VirtualFilesystem = .init(std.testing.allocator);
     defer vfs.deinit();
 
-    try db.to_zig(vfs.dir(), .{});
+    try to_zig(db, vfs.dir(), .{});
     try expect_output(&.{
         .{
             .path = "ATmega328P.zig",
@@ -2806,17 +2776,11 @@ test "gen.register with count and fields" {
         },
         .{
             .path = "types.zig",
-            .content =
-            \\pub const peripherals = @import("types/peripherals.zig");
-            \\
-            ,
+            .content = "pub const peripherals = @import(\"types/peripherals.zig\");\n",
         },
         .{
             .path = "peripherals.zig",
-            .content =
-            \\pub const PORTB = @import("peripherals/PORTB.zig").PORTB;
-            \\
-            ,
+            .content = "pub const PORTB = @import(\"peripherals/PORTB.zig\").PORTB;\n",
         },
         .{
             .path = "peripherals/PORTB.zig",
@@ -2831,11 +2795,14 @@ test "gen.register with count and fields" {
             \\    PORTB: [4]mmio.Mmio(packed struct(u8) {
             \\        TEST_FIELD: u4,
             \\        padding: u4 = 0,
+            \\    }, .{
+            \\        .TEST_FIELD = .read_write,
+            \\        .padding = .reserved,
             \\    }),
             \\    /// offset: 0x04
-            \\    DDRB: u8,
+            \\    DDRB: mmio.Mmio(u8, .read_write),
             \\    /// offset: 0x05
-            \\    PINB: u8,
+            \\    PINB: mmio.Mmio(u8, .read_write),
             \\};
             \\
             ,
@@ -2853,21 +2820,15 @@ test "gen.field with count, width of one, offset, and padding" {
     var vfs: VirtualFilesystem = .init(std.testing.allocator);
     defer vfs.deinit();
 
-    try db.to_zig(vfs.dir(), .{});
+    try to_zig(db, vfs.dir(), .{});
     try expect_output(&.{
         .{
             .path = "types.zig",
-            .content =
-            \\pub const peripherals = @import("types/peripherals.zig");
-            \\
-            ,
+            .content = "pub const peripherals = @import(\"types/peripherals.zig\");\n",
         },
         .{
             .path = "peripherals.zig",
-            .content =
-            \\pub const PORTB = @import("peripherals/PORTB.zig").PORTB;
-            \\
-            ,
+            .content = "pub const PORTB = @import(\"peripherals/PORTB.zig\").PORTB;\n",
         },
         .{
             .path = "peripherals/PORTB.zig",
@@ -2887,6 +2848,14 @@ test "gen.field with count, width of one, offset, and padding" {
             \\        TEST_FIELD3: u1,
             \\        TEST_FIELD4: u1,
             \\        padding: u1 = 0,
+            \\    }, .{
+            \\        .reserved2 = .reserved,
+            \\        .TEST_FIELD0 = .read_write,
+            \\        .TEST_FIELD1 = .read_write,
+            \\        .TEST_FIELD2 = .read_write,
+            \\        .TEST_FIELD3 = .read_write,
+            \\        .TEST_FIELD4 = .read_write,
+            \\        .padding = .reserved,
             \\    }),
             \\};
             \\
@@ -2905,21 +2874,15 @@ test "gen.field with count, multi-bit width, offset, and padding" {
     var vfs: VirtualFilesystem = .init(std.testing.allocator);
     defer vfs.deinit();
 
-    try db.to_zig(vfs.dir(), .{});
+    try to_zig(db, vfs.dir(), .{});
     try expect_output(&.{
         .{
             .path = "types.zig",
-            .content =
-            \\pub const peripherals = @import("types/peripherals.zig");
-            \\
-            ,
+            .content = "pub const peripherals = @import(\"types/peripherals.zig\");\n",
         },
         .{
             .path = "peripherals.zig",
-            .content =
-            \\pub const PORTB = @import("peripherals/PORTB.zig").PORTB;
-            \\
-            ,
+            .content = "pub const PORTB = @import(\"peripherals/PORTB.zig\").PORTB;\n",
         },
         .{
             .path = "peripherals/PORTB.zig",
@@ -2936,6 +2899,11 @@ test "gen.field with count, multi-bit width, offset, and padding" {
             \\        TEST_FIELD0: u2,
             \\        TEST_FIELD1: u2,
             \\        padding: u2 = 0,
+            \\    }, .{
+            \\        .reserved2 = .reserved,
+            \\        .TEST_FIELD0 = .read_write,
+            \\        .TEST_FIELD1 = .read_write,
+            \\        .padding = .reserved,
             \\    }),
             \\};
             \\
@@ -2954,7 +2922,7 @@ test "gen.interrupts.avr" {
     var vfs: VirtualFilesystem = .init(std.testing.allocator);
     defer vfs.deinit();
 
-    try db.to_zig(vfs.dir(), .{});
+    try to_zig(db, vfs.dir(), .{});
     try expect_output(&.{
         .{
             .path = "ATmega328P.zig",
@@ -3005,16 +2973,11 @@ test "gen.interrupts.avr" {
         },
         .{
             .path = "types.zig",
-            .content =
-            \\pub const peripherals = @import("types/peripherals.zig");
-            \\
-            ,
+            .content = "pub const peripherals = @import(\"types/peripherals.zig\");\n",
         },
         .{
             .path = "peripherals.zig",
-            .content =
-            \\
-            ,
+            .content = "",
         },
     }, &vfs);
 }
@@ -3029,21 +2992,15 @@ test "gen.peripheral type with register and field" {
     var vfs: VirtualFilesystem = .init(std.testing.allocator);
     defer vfs.deinit();
 
-    try db.to_zig(vfs.dir(), .{});
+    try to_zig(db, vfs.dir(), .{});
     try expect_output(&.{
         .{
             .path = "types.zig",
-            .content =
-            \\pub const peripherals = @import("types/peripherals.zig");
-            \\
-            ,
+            .content = "pub const peripherals = @import(\"types/peripherals.zig\");\n",
         },
         .{
             .path = "peripherals.zig",
-            .content =
-            \\pub const TEST_PERIPHERAL = @import("peripherals/TEST_PERIPHERAL.zig").TEST_PERIPHERAL;
-            \\
-            ,
+            .content = "pub const TEST_PERIPHERAL = @import(\"peripherals/TEST_PERIPHERAL.zig\").TEST_PERIPHERAL;\n",
         },
         .{
             .path = "peripherals/TEST_PERIPHERAL.zig",
@@ -3061,6 +3018,9 @@ test "gen.peripheral type with register and field" {
             \\        /// test field
             \\        TEST_FIELD: u1,
             \\        padding: u31 = 0,
+            \\    }, .{
+            \\        .TEST_FIELD = .read_write,
+            \\        .padding = .reserved,
             \\    }),
             \\};
             \\
@@ -3079,21 +3039,15 @@ test "gen.name collisions in enum name cause them to be anonymous" {
     var vfs: VirtualFilesystem = .init(std.testing.allocator);
     defer vfs.deinit();
 
-    try db.to_zig(vfs.dir(), .{});
+    try to_zig(db, vfs.dir(), .{});
     try expect_output(&.{
         .{
             .path = "types.zig",
-            .content =
-            \\pub const peripherals = @import("types/peripherals.zig");
-            \\
-            ,
+            .content = "pub const peripherals = @import(\"types/peripherals.zig\");\n",
         },
         .{
             .path = "peripherals.zig",
-            .content =
-            \\pub const TEST_PERIPHERAL = @import("peripherals/TEST_PERIPHERAL.zig").TEST_PERIPHERAL;
-            \\
-            ,
+            .content = "pub const TEST_PERIPHERAL = @import(\"peripherals/TEST_PERIPHERAL.zig\").TEST_PERIPHERAL;\n",
         },
         .{
             .path = "peripherals/TEST_PERIPHERAL.zig",
@@ -3116,6 +3070,9 @@ test "gen.name collisions in enum name cause them to be anonymous" {
             \\            TEST_ENUM_FIELD2 = 0x1,
             \\            _,
             \\        },
+            \\    }, .{
+            \\        .TEST_FIELD1 = .read_write,
+            \\        .TEST_FIELD2 = .read_write,
             \\    }),
             \\};
             \\
@@ -3134,21 +3091,15 @@ test "gen.pick one enum field in value collisions" {
     var vfs: VirtualFilesystem = .init(std.testing.allocator);
     defer vfs.deinit();
 
-    try db.to_zig(vfs.dir(), .{});
+    try to_zig(db, vfs.dir(), .{});
     try expect_output(&.{
         .{
             .path = "types.zig",
-            .content =
-            \\pub const peripherals = @import("types/peripherals.zig");
-            \\
-            ,
+            .content = "pub const peripherals = @import(\"types/peripherals.zig\");\n",
         },
         .{
             .path = "peripherals.zig",
-            .content =
-            \\pub const TEST_PERIPHERAL = @import("peripherals/TEST_PERIPHERAL.zig").TEST_PERIPHERAL;
-            \\
-            ,
+            .content = "pub const TEST_PERIPHERAL = @import(\"peripherals/TEST_PERIPHERAL.zig\").TEST_PERIPHERAL;\n",
         },
         .{
             .path = "peripherals/TEST_PERIPHERAL.zig",
@@ -3166,6 +3117,9 @@ test "gen.pick one enum field in value collisions" {
             \\            _,
             \\        },
             \\        padding: u4 = 0,
+            \\    }, .{
+            \\        .TEST_FIELD = .read_write,
+            \\        .padding = .reserved,
             \\    }),
             \\};
             \\
@@ -3184,7 +3138,7 @@ test "gen.pick one enum field in value collisions" {
 //    var vfs: VirtualFilesystem = .init(std.testing.allocator);
 //    defer vfs.deinit();
 //
-//    try db.to_zig(vfs.dir(), .{});
+//    try to_zig(db, vfs.dir(), .{});
 //    try expect_output(&.{
 //        .{
 //            .path = "types.zig",
@@ -3216,6 +3170,9 @@ test "gen.pick one enum field in value collisions" {
 //            \\            _,
 //            \\        },
 //            \\        padding: u4 = 0,
+//            \\    }, .{
+//            \\        .TEST_FIELD = .read_write,
+//            \\        .padding = .reserved,
 //            \\    }),
 //            \\};
 //            \\
@@ -3234,7 +3191,7 @@ test "gen.pick one enum field in value collisions" {
 //    var vfs: VirtualFilesystem = .init(std.testing.allocator);
 //    defer vfs.deinit();
 //
-//    try db.to_zig(vfs.dir(), .{});
+//    try to_zig(db, vfs.dir(), .{});
 //    try expect_output(&.{
 //        .{
 //            .path = "types.zig",
@@ -3265,6 +3222,9 @@ test "gen.pick one enum field in value collisions" {
 //            \\        /// test field 1
 //            \\        TEST_FIELD: u1,
 //            \\        padding: u31 = 0,
+//            \\    }, .{
+//            \\        .TEST_FIELD = .read_write,
+//            \\        .padding = .reserved,
 //            \\    }),
 //            \\};
 //            \\
@@ -3283,21 +3243,15 @@ test "gen.nested struct field in a peripheral" {
     var vfs: VirtualFilesystem = .init(std.testing.allocator);
     defer vfs.deinit();
 
-    try db.to_zig(vfs.dir(), .{});
+    try to_zig(db, vfs.dir(), .{});
     try expect_output(&.{
         .{
             .path = "types.zig",
-            .content =
-            \\pub const peripherals = @import("types/peripherals.zig");
-            \\
-            ,
+            .content = "pub const peripherals = @import(\"types/peripherals.zig\");\n",
         },
         .{
             .path = "peripherals.zig",
-            .content =
-            \\pub const TEST_PERIPHERAL = @import("peripherals/TEST_PERIPHERAL.zig").TEST_PERIPHERAL;
-            \\
-            ,
+            .content = "pub const TEST_PERIPHERAL = @import(\"peripherals/TEST_PERIPHERAL.zig\").TEST_PERIPHERAL;\n",
         },
         .{
             .path = "peripherals/TEST_PERIPHERAL.zig",
@@ -3318,6 +3272,9 @@ test "gen.nested struct field in a peripheral" {
             \\            /// test field 1
             \\            TEST_FIELD: u1,
             \\            padding: u31 = 0,
+            \\        }, .{
+            \\            .TEST_FIELD = .read_write,
+            \\            .padding = .reserved,
             \\        }),
             \\    },
             \\};
@@ -3337,21 +3294,15 @@ test "gen.nested struct field in a peripheral that has a named type" {
     var vfs: VirtualFilesystem = .init(std.testing.allocator);
     defer vfs.deinit();
 
-    try db.to_zig(vfs.dir(), .{});
+    try to_zig(db, vfs.dir(), .{});
     try expect_output(&.{
         .{
             .path = "types.zig",
-            .content =
-            \\pub const peripherals = @import("types/peripherals.zig");
-            \\
-            ,
+            .content = "pub const peripherals = @import(\"types/peripherals.zig\");\n",
         },
         .{
             .path = "peripherals.zig",
-            .content =
-            \\pub const TEST_PERIPHERAL = @import("peripherals/TEST_PERIPHERAL.zig").TEST_PERIPHERAL;
-            \\
-            ,
+            .content = "pub const TEST_PERIPHERAL = @import(\"peripherals/TEST_PERIPHERAL.zig\").TEST_PERIPHERAL;\n",
         },
         .{
             .path = "peripherals/TEST_PERIPHERAL.zig",
@@ -3370,6 +3321,9 @@ test "gen.nested struct field in a peripheral that has a named type" {
             \\            /// test field 1
             \\            TEST_FIELD: u1,
             \\            padding: u31 = 0,
+            \\        }, .{
+            \\            .TEST_FIELD = .read_write,
+            \\            .padding = .reserved,
             \\        }),
             \\    };
             \\
@@ -3393,21 +3347,15 @@ test "gen.nested struct field in a peripheral with offset" {
     var vfs: VirtualFilesystem = .init(std.testing.allocator);
     defer vfs.deinit();
 
-    try db.to_zig(vfs.dir(), .{});
+    try to_zig(db, vfs.dir(), .{});
     try expect_output(&.{
         .{
             .path = "types.zig",
-            .content =
-            \\pub const peripherals = @import("types/peripherals.zig");
-            \\
-            ,
+            .content = "pub const peripherals = @import(\"types/peripherals.zig\");\n",
         },
         .{
             .path = "peripherals.zig",
-            .content =
-            \\pub const TEST_PERIPHERAL = @import("peripherals/TEST_PERIPHERAL.zig").TEST_PERIPHERAL;
-            \\
-            ,
+            .content = "pub const TEST_PERIPHERAL = @import(\"peripherals/TEST_PERIPHERAL.zig\").TEST_PERIPHERAL;\n",
         },
         .{
             .path = "peripherals/TEST_PERIPHERAL.zig",
@@ -3430,6 +3378,9 @@ test "gen.nested struct field in a peripheral with offset" {
             \\            /// test field 1
             \\            TEST_FIELD: u1,
             \\            padding: u31 = 0,
+            \\        }, .{
+            \\            .TEST_FIELD = .read_write,
+            \\            .padding = .reserved,
             \\        }),
             \\    },
             \\};
@@ -3449,21 +3400,15 @@ test "gen.nested struct field in nested struct field" {
     var vfs: VirtualFilesystem = .init(std.testing.allocator);
     defer vfs.deinit();
 
-    try db.to_zig(vfs.dir(), .{});
+    try to_zig(db, vfs.dir(), .{});
     try expect_output(&.{
         .{
             .path = "types.zig",
-            .content =
-            \\pub const peripherals = @import("types/peripherals.zig");
-            \\
-            ,
+            .content = "pub const peripherals = @import(\"types/peripherals.zig\");\n",
         },
         .{
             .path = "peripherals.zig",
-            .content =
-            \\pub const TEST_PERIPHERAL = @import("peripherals/TEST_PERIPHERAL.zig").TEST_PERIPHERAL;
-            \\
-            ,
+            .content = "pub const TEST_PERIPHERAL = @import(\"peripherals/TEST_PERIPHERAL.zig\").TEST_PERIPHERAL;\n",
         },
         .{
             .path = "peripherals/TEST_PERIPHERAL.zig",
@@ -3486,6 +3431,9 @@ test "gen.nested struct field in nested struct field" {
             \\                /// test field 1
             \\                TEST_FIELD: u1,
             \\                padding: u31 = 0,
+            \\            }, .{
+            \\                .TEST_FIELD = .read_write,
+            \\                .padding = .reserved,
             \\            }),
             \\        },
             \\    },
@@ -3506,21 +3454,15 @@ test "gen.nested struct field next to register" {
     var vfs: VirtualFilesystem = .init(std.testing.allocator);
     defer vfs.deinit();
 
-    try db.to_zig(vfs.dir(), .{});
+    try to_zig(db, vfs.dir(), .{});
     try expect_output(&.{
         .{
             .path = "types.zig",
-            .content =
-            \\pub const peripherals = @import("types/peripherals.zig");
-            \\
-            ,
+            .content = "pub const peripherals = @import(\"types/peripherals.zig\");\n",
         },
         .{
             .path = "peripherals.zig",
-            .content =
-            \\pub const TEST_PERIPHERAL = @import("peripherals/TEST_PERIPHERAL.zig").TEST_PERIPHERAL;
-            \\
-            ,
+            .content = "pub const TEST_PERIPHERAL = @import(\"peripherals/TEST_PERIPHERAL.zig\").TEST_PERIPHERAL;\n",
         },
         .{
             .path = "peripherals/TEST_PERIPHERAL.zig",
@@ -3539,6 +3481,9 @@ test "gen.nested struct field next to register" {
             \\            /// test field 1
             \\            TEST_FIELD: u1,
             \\            padding: u31 = 0,
+            \\        }, .{
+            \\            .TEST_FIELD = .read_write,
+            \\            .padding = .reserved,
             \\        }),
             \\    };
             \\
@@ -3551,6 +3496,9 @@ test "gen.nested struct field next to register" {
             \\        /// test field 1
             \\        TEST_FIELD: u1,
             \\        padding: u31 = 0,
+            \\    }, .{
+            \\        .TEST_FIELD = .read_write,
+            \\        .padding = .reserved,
             \\    }),
             \\};
             \\
diff --git a/tools/regz/src/main.zig b/tools/regz/src/main.zig
index 4a1cd79ad..797a4dda5 100644
--- a/tools/regz/src/main.zig
+++ b/tools/regz/src/main.zig
@@ -1,12 +1,13 @@
 const std = @import("std");
-const clap = @import("clap");
-const xml = @import("xml.zig");
-const Database = @import("Database.zig");
-const FS_Directory = @import("FS_Directory.zig");
-
 const ArenaAllocator = std.heap.ArenaAllocator;
 const Allocator = std.mem.Allocator;
-const assert = std.debug.assert;
+
+// const clap = @import("clap"); TODO: use clap
+const Database = @import("Database.zig");
+const FS_Directory = @import("FS_Directory.zig");
+const gen = @import("gen.zig");
+const Patch = @import("patch.zig").Patch;
+const xml = @import("xml.zig");
 
 pub const std_options = std.Options{
     .log_level = .warn,
@@ -150,19 +151,20 @@ fn main_impl() anyerror!void {
     defer db.destroy();
 
     for (args.patch_paths.items) |patch_path| {
-        const patch = try std.fs.cwd().readFileAllocOptions(allocator, patch_path, std.math.maxInt(u64), null, .@"1", 0);
-        defer allocator.free(patch);
+        const patch_text = try std.fs.cwd().readFileAllocOptions(allocator, patch_path, std.math.maxInt(u64), null, .@"1", 0);
+        defer allocator.free(patch_text);
 
         var diags: std.zon.parse.Diagnostics = .{};
-        defer diags.deinit(db.gpa);
-
-        db.apply_patch(patch, &diags) catch |err| {
-            if (err == error.ParseZon) {
-                std.log.err("Failed to parse zon patch file '{s}': {f}", .{ patch_path, diags });
-            }
+        defer diags.deinit(allocator);
 
+        const patches = std.zon.parse.fromSlice([]const Patch, allocator, patch_text, &diags, .{}) catch |err| {
+            std.log.err("Failed to parse zon patch file '{s}': {f}", .{ patch_path, diags });
             return err;
         };
+        defer std.zon.parse.free(allocator, patches);
+
+        for (patches) |patch|
+            try db.apply_patch(patch);
     }
 
     // arch dependent stuff
@@ -186,5 +188,15 @@ fn main_impl() anyerror!void {
     defer output_dir.close();
 
     var fs = FS_Directory.init(output_dir);
-    try db.to_zig(fs.directory(), .{});
+    try gen.to_zig(db, fs.directory(), .{});
+}
+
+test "all" {
+    @setEvalBranchQuota(2000);
+    _ = @import("analysis.zig");
+    _ = @import("format/atdf.zig");
+    _ = Database;
+    _ = @import("gen.zig");
+    _ = @import("format/svd.zig");
+    _ = @import("VirtualFilesystem.zig");
 }
diff --git a/tools/regz/src/mmio.zig b/tools/regz/src/mmio.zig
deleted file mode 100644
index 22714cfbb..000000000
--- a/tools/regz/src/mmio.zig
+++ /dev/null
@@ -1,49 +0,0 @@
-const std = @import("std");
-
-pub fn Mmio(comptime size: u8, comptime PackedT: type) type {
-    if ((size % 8) != 0)
-        @compileError("size must be divisible by 8!");
-
-    if (!std.math.isPowerOfTwo(size / 8))
-        @compileError("size must encode a power of two number of bytes!");
-
-    const IntT = std.meta.Int(.unsigned, size);
-
-    if (@sizeOf(PackedT) != (size / 8))
-        @compileError(std.fmt.comptimePrint("IntT and PackedT must have the same size!, they are {} and {} bytes respectively", .{ size / 8, @sizeOf(PackedT) }));
-
-    return extern struct {
-        const Self = @This();
-
-        raw: IntT,
-
-        pub const underlying_type = PackedT;
-
-        pub inline fn read(addr: *volatile Self) PackedT {
-            return @as(PackedT, @bitCast(addr.raw));
-        }
-
-        pub inline fn write(addr: *volatile Self, val: PackedT) void {
-            // This is a workaround for a compiler bug related to miscompilation
-            // If the tmp var is not used, result location will fuck things up
-            const tmp = @as(IntT, @bitCast(val));
-            addr.raw = tmp;
-        }
-
-        pub inline fn modify(addr: *volatile Self, fields: anytype) void {
-            var val = read(addr);
-            inline for (@typeInfo(@TypeOf(fields)).@"struct".fields) |field| {
-                @field(val, field.name) = @field(fields, field.name);
-            }
-            write(addr, val);
-        }
-
-        pub inline fn toggle(addr: *volatile Self, fields: anytype) void {
-            var val = read(addr);
-            inline for (@typeInfo(@TypeOf(fields)).@"struct".fields) |field| {
-                @field(val, field.name) = @field(val, field.name) ^ @field(fields, field.name);
-            }
-            write(addr, val);
-        }
-    };
-}
diff --git a/tools/regz/src/patch.zig b/tools/regz/src/patch.zig
index a95a4926f..311e74b33 100644
--- a/tools/regz/src/patch.zig
+++ b/tools/regz/src/patch.zig
@@ -1,24 +1,24 @@
 const std = @import("std");
-const Allocator = std.mem.Allocator;
 const Database = @import("Database.zig");
 const Arch = @import("arch.zig").Arch;
 
-pub const Type = struct {
-    pub const EnumField = struct {
-        name: []const u8,
-        description: ?[]const u8 = null,
-        value: u32,
-    };
+pub const Patch = union(enum) {
+    pub const Type = union(enum) {
+        pub const EnumField = struct {
+            name: []const u8,
+            description: ?[]const u8 = null,
+            value: u32,
+        };
 
-    pub const Enum = struct {
-        name: []const u8,
-        description: ?[]const u8 = null,
-        bitsize: u8,
-        fields: []const EnumField = &.{},
+        pub const Enum = struct {
+            description: ?[]const u8 = null,
+            bitsize: u8,
+            fields: []const EnumField = &.{},
+        };
+
+        @"enum": Enum,
     };
-};
 
-pub const Patch = union(enum) {
     override_arch: struct {
         device_name: []const u8,
         arch: Arch,
@@ -29,9 +29,16 @@ pub const Patch = union(enum) {
         value: []const u8,
         description: ?[]const u8 = null,
     },
-    add_enum: struct {
+    add_interrupt: struct {
+        device_name: []const u8,
+        idx: i32,
+        name: []const u8,
+        description: ?[]const u8 = null,
+    },
+    add_type: struct {
         parent: []const u8,
-        @"enum": Type.Enum,
+        type_name: []const u8,
+        type: Type,
     },
     /// The replaced type MUST be the same size. Bit or Byte size depends on the
     /// context
@@ -39,31 +46,25 @@ pub const Patch = union(enum) {
         of: []const u8,
         to: ?[]const u8,
     },
-    add_interrupt: struct {
-        device_name: []const u8,
-        idx: i32,
-        name: []const u8,
-        description: ?[]const u8 = null,
-    },
-    /// Creates a new enum type in the specified parent struct and applies it
+    /// Creates a new type in the specified parent struct and applies it
     /// to all the specified field references. This is a convenience patch that
-    /// combines `add_enum` with multiple `set_enum_type` operations.
-    add_enum_and_apply: struct {
+    /// combines `add_type` with multiple `set_enum_type` operations.
+    add_type_and_apply: struct {
         parent: []const u8,
-        @"enum": Type.Enum,
+        type_name: []const u8,
+        type: Type,
         apply_to: []const []const u8,
     },
-
-    pub fn from_json_str(allocator: Allocator, json_str: []const u8) !std.json.Parsed(Patch) {
-        return std.json.parseFromSlice(Patch, allocator, json_str, .{});
-    }
-};
-
-/// List for assembling patches in build scripts
-pub const PatchList = struct {
-    entries: std.array_list.Managed(Patch),
-
-    pub fn append(list: *PatchList, patch: Patch) void {
-        list.append(patch) catch @panic("OOM");
-    }
+    add_struct_field: struct {
+        parent: []const u8,
+        name: []const u8,
+        description: ?[]const u8 = null,
+        size_bits: u8,
+        offset_bits: u8,
+        access: Database.Access = .default,
+        type: union(enum) {
+            uint: u8,
+            @"enum": []const u8,
+        },
+    },
 };
diff --git a/tools/regz/src/module.zig b/tools/regz/src/root.zig
similarity index 67%
rename from tools/regz/src/module.zig
rename to tools/regz/src/root.zig
index afb4bbc8a..2f355bc32 100644
--- a/tools/regz/src/module.zig
+++ b/tools/regz/src/root.zig
@@ -1,7 +1,9 @@
-pub const Database = @import("Database.zig");
 pub const Analysis = @import("analysis.zig");
+pub const Arch = @import("arch.zig").Arch;
 pub const arm = @import("arch/arm.zig");
+pub const Database = @import("Database.zig");
+pub const Directory = @import("Directory.zig");
+pub const embassy = @import("format/embassy.zig");
+pub const gen = @import("gen.zig");
 pub const Patch = @import("patch.zig").Patch;
-pub const Arch = @import("arch.zig").Arch;
-pub const embassy = @import("embassy.zig");
 pub const VirtualFilesystem = @import("VirtualFilesystem.zig");
diff --git a/tools/sorcerer/src/RegzWindow.zig b/tools/sorcerer/src/RegzWindow.zig
index 34667b857..506d89d67 100644
--- a/tools/sorcerer/src/RegzWindow.zig
+++ b/tools/sorcerer/src/RegzWindow.zig
@@ -268,7 +268,7 @@ pub fn create(
         .register_schema_usages = register_schema_usages,
     };
 
-    try db.to_zig(window.vfs.dir(), .{});
+    try regz.gen.to_zig(db, window.vfs.dir(), .{});
 
     count += 1;
 
@@ -941,7 +941,7 @@ fn load_patch_files(w: *RegzWindow) void {
 
         // Apply patches to the database so analysis reflects them
         for (patches) |patch| {
-            apply_single_patch(w.db, alloc, patch) catch continue;
+            w.db.apply_patch(patch) catch continue;
         }
 
         const owned_path = alloc.dupe(u8, path) catch continue;
@@ -1058,10 +1058,11 @@ fn get_patch_label(patch: regz.Patch, arena: Allocator) []const u8 {
     return switch (patch) {
         .override_arch => |p| std.fmt.allocPrint(arena, "override_arch: {s}", .{p.device_name}) catch "override_arch",
         .set_device_property => |p| std.fmt.allocPrint(arena, "set_device_property: {s}", .{p.key}) catch "set_device_property",
-        .add_enum => |p| std.fmt.allocPrint(arena, "add_enum: {s}", .{p.@"enum".name}) catch "add_enum",
+        .add_type => |p| std.fmt.allocPrint(arena, "add_type: {t} {s}", .{ p.type, p.type_name }) catch "add_type",
         .set_enum_type => |p| std.fmt.allocPrint(arena, "set_enum_type: {s}", .{p.of}) catch "set_enum_type",
         .add_interrupt => |p| std.fmt.allocPrint(arena, "add_interrupt: {s}", .{p.name}) catch "add_interrupt",
-        .add_enum_and_apply => |p| std.fmt.allocPrint(arena, "add_enum_and_apply: {s}", .{p.@"enum".name}) catch "add_enum_and_apply",
+        .add_type_and_apply => |p| std.fmt.allocPrint(arena, "add_type_and_apply: {t} {s}", .{ p.type, p.type_name }) catch "add_type_and_apply",
+        .add_struct_field => |p| std.fmt.allocPrint(arena, "add_struct_field: {t} {s}", .{ p.type, p.name }) catch "add_struct_field",
     };
 }
 
@@ -1197,19 +1198,20 @@ fn show_patch_details(w: *RegzWindow, arena: Allocator) void {
             switch (patch) {
                 .override_arch => |p| show_override_arch_widget(p),
                 .set_device_property => |p| show_set_device_property_widget(p),
-                .add_enum => |p| show_add_enum_widget(p, arena),
+                .add_type => |p| show_add_type_widget(p, arena),
                 .set_enum_type => |p| show_set_enum_type_widget(p),
                 .add_interrupt => |p| show_add_interrupt_widget(p),
-                .add_enum_and_apply => |p| show_add_enum_and_apply_widget(p, arena),
+                .add_type_and_apply => |p| show_add_type_and_apply_widget(p, arena),
+                .add_struct_field => |p| show_add_struct_field_widget(p),
             }
         },
         .diff => {
-            w.show_patch_diff(arena, sel, patch);
+            w.show_patch_diff(sel, patch);
         },
     }
 }
 
-fn show_patch_diff(w: *RegzWindow, arena: Allocator, sel: SelectedPatch, patch: regz.Patch) void {
+fn show_patch_diff(w: *RegzWindow, sel: SelectedPatch, patch: regz.Patch) void {
     // Check if cache is valid
     if (w.cached_diff) |cached| {
         if (cached.file_index == sel.file_index and cached.patch_index == sel.patch_index) {
@@ -1227,7 +1229,7 @@ fn show_patch_diff(w: *RegzWindow, arena: Allocator, sel: SelectedPatch, patch:
     }
 
     // Compute new diff
-    w.compute_patch_diff(arena, sel, patch);
+    w.compute_patch_diff(sel, patch);
 
     // Display the newly computed diff
     if (w.cached_diff) |cached| {
@@ -1343,7 +1345,7 @@ fn display_diff(w: *RegzWindow, file_diffs: []const FileDiff, sel: SelectedPatch
     }
 }
 
-fn compute_patch_diff(w: *RegzWindow, temp_arena: Allocator, sel: SelectedPatch, patch: regz.Patch) void {
+fn compute_patch_diff(w: *RegzWindow, sel: SelectedPatch, patch: regz.Patch) void {
     _ = patch; // We'll get the patch from the loaded patches instead
     // Use window's persistent arena for cached data
     const arena = w.arena.allocator();
@@ -1395,23 +1397,17 @@ fn compute_patch_diff(w: *RegzWindow, temp_arena: Allocator, sel: SelectedPatch,
                 const is_selected_or_before = (file_idx < sel.file_index) or
                     (file_idx == sel.file_index and patch_idx <= sel.patch_index);
 
-                // Serialize this patch
-                var zon_buf: std.Io.Writer.Allocating = .init(temp_arena);
-                const patch_array: []const regz.Patch = &.{p};
-                std.zon.stringify.serialize(patch_array, .{}, &zon_buf.writer) catch continue;
-                const zon_text = temp_arena.dupeZ(u8, zon_buf.written()) catch continue;
-
                 var diags: std.zon.parse.Diagnostics = .{};
 
                 // Apply to before_db if this patch comes before the selected one
                 if (is_before_selected) {
-                    before_db.apply_patch(zon_text, &diags) catch continue;
+                    before_db.apply_patch(p) catch continue;
                 }
 
                 // Apply to after_db if this patch is the selected one or comes before it
                 if (is_selected_or_before) {
                     diags = .{};
-                    after_db.apply_patch(zon_text, &diags) catch continue;
+                    after_db.apply_patch(p) catch continue;
                 }
             }
         }
@@ -1425,23 +1421,14 @@ fn compute_patch_diff(w: *RegzWindow, temp_arena: Allocator, sel: SelectedPatch,
             const is_selected_or_before = (file_idx < sel.file_index) or
                 (file_idx == sel.file_index and full_idx <= sel.patch_index);
 
-            // Serialize this patch
-            var zon_buf: std.Io.Writer.Allocating = .init(temp_arena);
-            const patch_array: []const regz.Patch = &.{p};
-            std.zon.stringify.serialize(patch_array, .{}, &zon_buf.writer) catch continue;
-            const zon_text = temp_arena.dupeZ(u8, zon_buf.written()) catch continue;
-
-            var diags: std.zon.parse.Diagnostics = .{};
-
             // Apply to before_db if this patch comes before the selected one
             if (is_before_selected) {
-                before_db.apply_patch(zon_text, &diags) catch continue;
+                before_db.apply_patch(p) catch continue;
             }
 
             // Apply to after_db if this patch is the selected one or comes before it
             if (is_selected_or_before) {
-                diags = .{};
-                after_db.apply_patch(zon_text, &diags) catch continue;
+                after_db.apply_patch(p) catch continue;
             }
         }
     }
@@ -1450,7 +1437,7 @@ fn compute_patch_diff(w: *RegzWindow, temp_arena: Allocator, sel: SelectedPatch,
     var before_vfs: VirtualFilesystem = .init(w.gpa);
     defer before_vfs.deinit();
 
-    before_db.to_zig(before_vfs.dir(), .{}) catch |err| {
+    regz.gen.to_zig(before_db, before_vfs.dir(), .{}) catch |err| {
         w.cached_diff = .{
             .file_index = sel.file_index,
             .patch_index = sel.patch_index,
@@ -1464,7 +1451,7 @@ fn compute_patch_diff(w: *RegzWindow, temp_arena: Allocator, sel: SelectedPatch,
     var after_vfs: VirtualFilesystem = .init(w.gpa);
     defer after_vfs.deinit();
 
-    after_db.to_zig(after_vfs.dir(), .{}) catch |err| {
+    regz.gen.to_zig(after_db, after_vfs.dir(), .{}) catch |err| {
         w.cached_diff = .{
             .file_index = sel.file_index,
             .patch_index = sel.patch_index,
@@ -1701,80 +1688,82 @@ fn show_set_device_property_widget(p: anytype) void {
     if (p.description) |desc| labeled_field("Description", desc);
 }
 
-fn show_add_enum_widget(p: anytype, arena: Allocator) void {
+fn show_add_type_widget(p: anytype, arena: Allocator) void {
     labeled_field("Parent", p.parent);
-    show_enum_details(p.@"enum", arena);
+    show_type_details(p, arena);
 }
 
-fn show_enum_details(e: anytype, arena: Allocator) void {
-    labeled_field("Name", e.name);
-    if (e.description) |d| labeled_field("Description", d);
-    const bitsize_str = std.fmt.allocPrint(arena, "{d}", .{e.bitsize}) catch "?";
+fn show_type_details(p: anytype, arena: Allocator) void {
+    labeled_field("Name", p.type_name);
+    if (p.type.@"enum".description) |d| labeled_field("Description", d);
+    const bitsize_str = std.fmt.allocPrint(arena, "{d}", .{p.type.@"enum".bitsize}) catch "?";
     labeled_field("Bit Size", bitsize_str);
 
     _ = dvui.spacer(@src(), .{ .min_size_content = .{ .h = 8 } });
 
-    if (e.fields.len > 0) {
-        _ = dvui.label(@src(), "Fields:", .{}, .{
-            .font = .{ .weight = .bold },
-            .color_text = dvui.Color.fromHex("FBB829"),
-        });
+    switch (p.type) {
+        .@"enum" => |e| if (e.fields.len > 0) {
+            _ = dvui.label(@src(), "Fields:", .{}, .{
+                .font = .{ .weight = .bold },
+                .color_text = dvui.Color.fromHex("FBB829"),
+            });
 
-        _ = dvui.spacer(@src(), .{ .min_size_content = .{ .h = 4 } });
+            _ = dvui.spacer(@src(), .{ .min_size_content = .{ .h = 4 } });
 
-        // Table for enum fields
-        const header_style: dvui.GridWidget.CellStyle = .{
-            .cell_opts = .{
-                .border = .{ .y = 0, .h = 1, .x = 0, .w = 0 },
-            },
-        };
+            // Table for enum fields
+            const header_style: dvui.GridWidget.CellStyle = .{
+                .cell_opts = .{
+                    .border = .{ .y = 0, .h = 1, .x = 0, .w = 0 },
+                },
+            };
 
-        // Column widths: Name (120 fixed), Value (60 fixed), Description (proportional -1)
-        var col_widths: [3]f32 = .{ 0, 0, 0 };
-        var grid = dvui.grid(@src(), .{ .col_widths = &col_widths }, .{}, .{
-            .expand = .both,
-            .background = true,
-            .padding = dvui.Rect.all(4),
-        });
-        defer grid.deinit();
+            // Column widths: Name (120 fixed), Value (60 fixed), Description (proportional -1)
+            var col_widths: [3]f32 = .{ 0, 0, 0 };
+            var grid = dvui.grid(@src(), .{ .col_widths = &col_widths }, .{}, .{
+                .expand = .both,
+                .background = true,
+                .padding = dvui.Rect.all(4),
+            });
+            defer grid.deinit();
 
-        // Layout: fixed 120 for Name, fixed 60 for Value, rest for Description
-        dvui.columnLayoutProportional(&.{ 120, 60, -1 }, &col_widths, grid.data().contentRect().w);
+            // Layout: fixed 120 for Name, fixed 60 for Value, rest for Description
+            dvui.columnLayoutProportional(&.{ 120, 60, -1 }, &col_widths, grid.data().contentRect().w);
 
-        // Table headers
-        dvui.gridHeading(@src(), grid, 0, "Name", .fixed, header_style);
-        dvui.gridHeading(@src(), grid, 1, "Value", .fixed, header_style);
-        dvui.gridHeading(@src(), grid, 2, "Description", .fixed, header_style);
+            // Table headers
+            dvui.gridHeading(@src(), grid, 0, "Name", .fixed, header_style);
+            dvui.gridHeading(@src(), grid, 1, "Value", .fixed, header_style);
+            dvui.gridHeading(@src(), grid, 2, "Description", .fixed, header_style);
 
-        // Table rows
-        for (e.fields, 0..) |field, row_num| {
-            var cell_num: dvui.GridWidget.Cell = .colRow(0, row_num);
+            // Table rows
+            for (e.fields, 0..) |field, row_num| {
+                var cell_num: dvui.GridWidget.Cell = .colRow(0, row_num);
 
-            // Name column
-            {
-                defer cell_num.col_num += 1;
-                var cell = grid.bodyCell(@src(), cell_num, .{});
-                defer cell.deinit();
-                dvui.labelNoFmt(@src(), field.name, .{}, .{});
-            }
+                // Name column
+                {
+                    defer cell_num.col_num += 1;
+                    var cell = grid.bodyCell(@src(), cell_num, .{});
+                    defer cell.deinit();
+                    dvui.labelNoFmt(@src(), field.name, .{}, .{});
+                }
 
-            // Value column
-            {
-                defer cell_num.col_num += 1;
-                var cell = grid.bodyCell(@src(), cell_num, .{});
-                defer cell.deinit();
-                const value_str = std.fmt.allocPrint(arena, "{d}", .{field.value}) catch "?";
-                dvui.labelNoFmt(@src(), value_str, .{}, .{});
-            }
+                // Value column
+                {
+                    defer cell_num.col_num += 1;
+                    var cell = grid.bodyCell(@src(), cell_num, .{});
+                    defer cell.deinit();
+                    const value_str = std.fmt.allocPrint(arena, "{d}", .{field.value}) catch "?";
+                    dvui.labelNoFmt(@src(), value_str, .{}, .{});
+                }
 
-            // Description column
-            {
-                defer cell_num.col_num += 1;
-                var cell = grid.bodyCell(@src(), cell_num, .{});
-                defer cell.deinit();
-                dvui.labelNoFmt(@src(), field.description orelse "", .{}, .{});
+                // Description column
+                {
+                    defer cell_num.col_num += 1;
+                    var cell = grid.bodyCell(@src(), cell_num, .{});
+                    defer cell.deinit();
+                    dvui.labelNoFmt(@src(), field.description orelse "", .{}, .{});
+                }
             }
-        }
+        },
     }
 }
 
@@ -1792,9 +1781,9 @@ fn show_add_interrupt_widget(p: anytype) void {
     if (p.description) |d| labeled_field("Description", d);
 }
 
-fn show_add_enum_and_apply_widget(p: anytype, arena: Allocator) void {
+fn show_add_type_and_apply_widget(p: anytype, arena: Allocator) void {
     labeled_field("Parent", p.parent);
-    show_enum_details(p.@"enum", arena);
+    show_type_details(p, arena);
 
     _ = dvui.spacer(@src(), .{ .min_size_content = .{ .h = 8 } });
 
@@ -1810,6 +1799,12 @@ fn show_add_enum_and_apply_widget(p: anytype, arena: Allocator) void {
     }
 }
 
+fn show_add_struct_field_widget(p: anytype) void {
+    labeled_field("Parent", p.parent);
+    labeled_field("Name", p.name);
+    // TODO: more
+}
+
 fn labeled_field(label_text: []const u8, value: []const u8) void {
     // Use hash of label text as unique ID to avoid duplicate widget IDs
     const label_hash = std.hash.Wyhash.hash(0, label_text);
@@ -2133,7 +2128,7 @@ fn show_create_patch_dialog_ui(w: *RegzWindow, arena: Allocator) void {
             .color_text = if (can_create) dvui.Color.fromHex("1C1B19") else dvui.Color.fromHex("918175"),
         }) and can_create) {
             // Create the patch
-            w.create_patch_from_group(arena, pending.*) catch |err| {
+            w.create_patch_from_group(pending.*) catch |err| {
                 w.validation_error_message = std.fmt.allocPrint(w.arena.allocator(), "Failed to create patch: {s}", .{@errorName(err)}) catch "Failed to create patch";
                 w.show_validation_error = true;
             };
@@ -2144,7 +2139,7 @@ fn show_create_patch_dialog_ui(w: *RegzWindow, arena: Allocator) void {
 }
 
 /// Create a patch from an equivalence group
-fn create_patch_from_group(w: *RegzWindow, arena: Allocator, pending: PendingPatchCreation) !void {
+fn create_patch_from_group(w: *RegzWindow, pending: PendingPatchCreation) !void {
     // Get the cached analysis result
     const cached = w.cached_analysis orelse return error.NoAnalysis;
 
@@ -2169,8 +2164,8 @@ fn create_patch_from_group(w: *RegzWindow, arena: Allocator, pending: PendingPat
     const enum_name = std.mem.sliceTo(&pending.enum_name_buffer, 0);
     if (enum_name.len == 0) return error.EmptyEnumName;
 
-    // Create the add_enum_and_apply patch
-    const patch = try create_add_enum_and_apply_patch(
+    // Create the add_type_and_apply patch
+    const patch = try create_add_type_and_apply_patch(
         w.arena.allocator(),
         pending.peripheral_name,
         enum_name,
@@ -2190,7 +2185,7 @@ fn create_patch_from_group(w: *RegzWindow, arena: Allocator, pending: PendingPat
     w.has_unsaved_patches = true;
 
     // Apply the patch to the database so analysis reflects the change
-    try apply_single_patch(w.db, arena, patch);
+    try w.db.apply_patch(patch);
 
     // Refresh all views that depend on the database
     w.on_database_changed();
@@ -2246,21 +2241,17 @@ fn rebuild_database_with_patches(w: *RegzWindow) void {
         return;
     };
 
-    const alloc = w.arena.allocator();
-
     // Reapply all non-deleted patches from all files
     for (w.loaded_patches.values()) |loaded| {
         if (loaded.patches) |patches| {
             for (patches, 0..) |patch, idx| {
-                if (!loaded.is_patch_deleted(idx)) {
-                    apply_single_patch(w.db, alloc, patch) catch continue;
-                }
+                if (!loaded.is_patch_deleted(idx))
+                    w.db.apply_patch(patch) catch continue;
             }
         }
         // Reapply pending patches
-        for (loaded.pending_patches.items) |patch| {
-            apply_single_patch(w.db, alloc, patch) catch continue;
-        }
+        for (loaded.pending_patches.items) |patch|
+            w.db.apply_patch(patch) catch continue;
     }
 
     // Refresh all views that depend on the database
@@ -2274,7 +2265,7 @@ fn on_database_changed(w: *RegzWindow) void {
     // Deinit old VFS and create new one
     w.vfs.deinit();
     w.vfs = .init(w.gpa);
-    w.db.to_zig(w.vfs.dir(), .{}) catch |err| {
+    regz.gen.to_zig(w.db, w.vfs.dir(), .{}) catch |err| {
         std.log.err("Failed to regenerate code: {}", .{err});
     };
 
@@ -2289,8 +2280,8 @@ fn on_database_changed(w: *RegzWindow) void {
     w.cached_diff = null;
 }
 
-/// Create an add_enum_and_apply patch from an equivalence group
-fn create_add_enum_and_apply_patch(
+/// Create an add_type_and_apply patch from an equivalence group
+fn create_add_type_and_apply_patch(
     alloc: Allocator,
     peripheral_name: []const u8,
     enum_name: []const u8,
@@ -2300,8 +2291,8 @@ fn create_add_enum_and_apply_patch(
     const parent = try std.fmt.allocPrint(alloc, "types.peripherals.{s}", .{peripheral_name});
 
     // Get the EnumField type from the Patch type using type introspection
-    const AddEnumAndApply = std.meta.TagPayload(regz.Patch, .add_enum_and_apply);
-    const EnumType = @TypeOf(@as(AddEnumAndApply, undefined).@"enum");
+    const AddEnumAndApply = std.meta.TagPayload(regz.Patch, .add_type_and_apply);
+    const EnumType = @TypeOf(@as(AddEnumAndApply, undefined).type.@"enum");
     const EnumFieldType = std.meta.Child(@TypeOf(@as(EnumType, undefined).fields));
 
     // Convert fields (note: Database.EnumField.value is u64, Patch.EnumField.value is u32)
@@ -2325,14 +2316,14 @@ fn create_add_enum_and_apply_patch(
     }
 
     return .{
-        .add_enum_and_apply = .{
+        .add_type_and_apply = .{
             .parent = parent,
-            .@"enum" = .{
-                .name = try alloc.dupe(u8, enum_name),
+            .type_name = try alloc.dupe(u8, enum_name),
+            .type = .{ .@"enum" = .{
                 .description = if (group.description) |d| try alloc.dupe(u8, d) else null,
                 .bitsize = group.size_bits,
                 .fields = fields,
-            },
+            } },
             .apply_to = apply_to,
         },
     };
@@ -2559,27 +2550,14 @@ fn validate_patch_file(w: *RegzWindow, arena: Allocator, patch_path: []const u8,
     // Apply original patches (excluding deleted ones)
     if (loaded.patches) |patches| {
         for (patches, 0..) |patch, idx| {
-            if (!loaded.is_patch_deleted(idx)) {
-                try apply_single_patch(db, arena, patch);
-            }
+            if (!loaded.is_patch_deleted(idx))
+                try db.apply_patch(patch);
         }
     }
 
     // Apply pending patches
-    for (loaded.pending_patches.items) |patch| {
-        try apply_single_patch(db, arena, patch);
-    }
-}
-
-/// Apply a single patch to a database
-fn apply_single_patch(db: *regz.Database, arena: Allocator, patch: regz.Patch) !void {
-    var zon_buf: std.Io.Writer.Allocating = .init(arena);
-    const patch_array: []const regz.Patch = &.{patch};
-    try std.zon.stringify.serialize(patch_array, .{}, &zon_buf.writer);
-    const zon_text = try arena.dupeZ(u8, zon_buf.written());
-
-    var diags: std.zon.parse.Diagnostics = .{};
-    try db.apply_patch(zon_text, &diags);
+    for (loaded.pending_patches.items) |patch|
+        try db.apply_patch(patch);
 }
 
 /// Write a patch file combining original (non-deleted) and pending patches
diff --git a/tools/sorcerer/src/cli.zig b/tools/sorcerer/src/cli.zig
index 88fae6225..3e991f755 100644
--- a/tools/sorcerer/src/cli.zig
+++ b/tools/sorcerer/src/cli.zig
@@ -365,7 +365,7 @@ fn generate_code(
     var vfs = regz.VirtualFilesystem.init(allocator);
     defer vfs.deinit();
 
-    db.to_zig(vfs.dir(), .{}) catch |err| {
+    regz.gen.to_zig(db, vfs.dir(), .{}) catch |err| {
         try stderr.print("Error generating Zig code: {}\n", .{err});
         try stderr.flush();
         return error.Explained;
diff --git a/tools/sorcerer/src/test_diff.zig b/tools/sorcerer/src/test_diff.zig
index 1a1ecc5b2..b0be3495f 100644
--- a/tools/sorcerer/src/test_diff.zig
+++ b/tools/sorcerer/src/test_diff.zig
@@ -283,16 +283,16 @@ const TestEnumField = struct {
 };
 
 const TestEnum = struct {
-    name: []const u8,
     description: ?[]const u8 = null,
     bitsize: u8,
     fields: []const TestEnumField = &.{},
 };
 
 const TestPatch = union(enum) {
-    add_enum_and_apply: struct {
+    add_type_and_apply: struct {
         parent: []const u8,
-        @"enum": TestEnum,
+        type_name: []const u8,
+        type: union(enum) { @"enum": TestEnum },
         apply_to: []const []const u8,
     },
 };
@@ -302,17 +302,17 @@ test "zon serialize single patch - raw output" {
     defer arena.deinit();
     const allocator = arena.allocator();
 
-    const patch = TestPatch{ .add_enum_and_apply = .{
+    const patch = TestPatch{ .add_type_and_apply = .{
         .parent = "types.peripherals.TEST",
-        .@"enum" = .{
-            .name = "TestEnum",
+        .type_name = "TestEnum",
+        .type = .{ .@"enum" = .{
             .description = null,
             .bitsize = 2,
             .fields = &.{
                 .{ .name = "val0", .description = null, .value = 0 },
                 .{ .name = "val1", .description = null, .value = 1 },
             },
-        },
+        } },
         .apply_to = &.{
             "types.peripherals.TEST.REG1.FIELD",
             "types.peripherals.TEST.REG2.FIELD",
@@ -328,7 +328,7 @@ test "zon serialize single patch - raw output" {
     std.debug.print("\n=== Raw ZON output (single patch) ===\n{s}\n=== End ===\n", .{output});
 
     // Check that the output contains expected content
-    try std.testing.expect(std.mem.indexOf(u8, output, "add_enum_and_apply") != null);
+    try std.testing.expect(std.mem.indexOf(u8, output, "add_type_and_apply") != null);
     try std.testing.expect(std.mem.indexOf(u8, output, "TestEnum") != null);
 }
 
@@ -337,25 +337,25 @@ test "zon serialize multiple patches - raw output" {
     defer arena.deinit();
     const allocator = arena.allocator();
 
-    const patch1 = TestPatch{ .add_enum_and_apply = .{
+    const patch1 = TestPatch{ .add_type_and_apply = .{
         .parent = "types.peripherals.TEST1",
-        .@"enum" = .{
-            .name = "Enum1",
+        .type_name = "Enum1",
+        .type = .{ .@"enum" = .{
             .description = null,
             .bitsize = 2,
             .fields = &.{},
-        },
+        } },
         .apply_to = &.{},
     } };
 
-    const patch2 = TestPatch{ .add_enum_and_apply = .{
+    const patch2 = TestPatch{ .add_type_and_apply = .{
         .parent = "types.peripherals.TEST2",
-        .@"enum" = .{
-            .name = "Enum2",
+        .type_name = "Enum2",
+        .type = .{ .@"enum" = .{
             .description = null,
             .bitsize = 2,
             .fields = &.{},
-        },
+        } },
         .apply_to = &.{},
     } };