https://github.com/T-head-Semi/openc906/raw/main/doc/%E7%8E%84%E9%93%81C906%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C.pdf
Found some issues in the programming manual that is inconsistent with RISCV spec.
Are those documentation only errors?
Page 150 (Page 167 in the PDF)
FDIV.S
it says fs1 in [24:20], fs2 in [19:15],
but it should be fs2 in [24:20], fs1 in [19:15]
Page 194 (Page 211 in the PDF)
C.FLD
it says [15:13] is 011, which should be 001
Page 201
C.LUI
it says rd ! = 0, which should be rd != 0 && rd != 2,
otherwise it would be ambiguous with C.ADDI16SP
Page 205
C.SD
In instruction encoding, rd should be rs2
https://github.com/T-head-Semi/openc906/raw/main/doc/%E7%8E%84%E9%93%81C906%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C.pdf
Found some issues in the programming manual that is inconsistent with RISCV spec.
Are those documentation only errors?
Page 150 (Page 167 in the PDF)
FDIV.S
it says
fs1in [24:20],fs2in [19:15],but it should be
fs2in [24:20],fs1in [19:15]Page 194 (Page 211 in the PDF)
C.FLD
it says [15:13] is
011, which should be001Page 201
C.LUI
it says
rd ! = 0, which should berd != 0 && rd != 2,otherwise it would be ambiguous with C.ADDI16SP
Page 205
C.SD
In
instruction encoding,rdshould bers2