Request flag to turn off optimization in verilog input

[FrancisAndCo]

PyRTL has been super helpful on one of my projects because of its representation of Verilog. We're trying to use PyRTL to do robustness analysis on circuits with triple modular redundancy (TMR). Currently input_from_verilog calls yosys with the flags synth and opt forcing multiple optimization passes. However when there is full path redundancy, yosys output will automatically optimize out the desired TMR tracks or cause an error.

I wrote a workaround locally that has a second function
input_from_verilog_noopt omits the calls to opt while retaining most of the pipeline from synth. However I think there is some reasonable space to add some support for user provided yosys flags.

Problem:

• input_from_verilog currently automatically optimizes out logically equivalent TMR paths or errors out due to undriven wires.

Potential fix:

• provide optional argument to input_from_verilog that will turn off
  optimization in yosys.

Alternatively, there could be a desire to pass flags through to yosys,
but this is a more heavyweight solution.
I could make PR for this, are you interested in having this modification
in PyRTL?

[fdxmw]

Hello and thank you for your interest in PyRTL!

I generally prefer to keep things simple, so I'd rather not add a new option, unless:

1. Something is impossible, or prohibitively difficult, without the new option, or
2. The new option would lift a burden from multiple users.

For (1), PyRTL already provides the lower-level input_from_blif, so you can write your own yosys script without optimization, and pass the resulting blif file to input_from_blif. It sounds like you're already doing this.

For (2), input_from_verilog doesn't seem to have many users (a GitHub code search shows ~1 call outside of PyRTL itself), and disabling optimization sounds like a fairly uncommon need to me, so it seems pretty unlikely that adding this new option would help multiple users.

So I'm inclined to keep things as they are: you are free to continue using your version of input_from_verilog that disables yosys optimization, and that code should live in your project's repository, not PyRTL's.

I'd be happy to take a look at a PR, but you'll need to convince me that someone other than yourself will find the new code useful before I'll merge it :) It seems quite tricky to design a new option that's both

• Generally useful (a disable_yosys_optimization bool seems too narrow), and
• Shields the user from writing a yosys script (if the user knows how to do that, they can use input_from_blif)