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Merge pull request #3896 from The-OpenROAD-Project-staging/test-orfs-update-owned-designs
update owned designs config and metrics update
2 parents 4747b79 + 671dc5a commit e3f6ead

12 files changed

Lines changed: 65 additions & 71 deletions

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flow/designs/asap7/aes-block/config.mk

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,10 +8,9 @@ export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.
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export ABC_AREA = 1
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11-
export CORE_UTILIZATION = 40
11+
export CORE_UTILIZATION = 47
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export CORE_ASPECT_RATIO = 1
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export CORE_MARGIN = 2
14-
export PLACE_DENSITY = 0.53
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export BLOCKS ?= aes_rcon aes_sbox
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export SYNTH_HIERARCHICAL = 1

flow/designs/asap7/aes-block/rules-base.json

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -12,27 +12,27 @@
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"compare": "<="
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},
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"placeopt__design__instance__count__stdcell": {
15-
"value": 10573,
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"value": 10501,
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"compare": "<="
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},
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"detailedplace__design__violations": {
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"value": 0,
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"compare": "=="
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},
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"cts__design__instance__count__setup_buffer": {
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"value": 919,
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"value": 913,
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"compare": "<="
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},
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"cts__design__instance__count__hold_buffer": {
27-
"value": 1286,
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"value": 1691,
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"compare": "<="
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},
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"cts__timing__setup__ws": {
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"value": -148.0,
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"compare": ">="
3333
},
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"cts__timing__setup__tns": {
35-
"value": -7820.0,
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"value": -12100.0,
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"compare": ">="
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},
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"cts__timing__hold__ws": {
@@ -48,11 +48,11 @@
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"compare": "<="
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},
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"globalroute__timing__setup__ws": {
51-
"value": -150.0,
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"value": -133.0,
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"compare": ">="
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},
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"globalroute__timing__setup__tns": {
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"value": -6750.0,
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"value": -9610.0,
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"compare": ">="
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},
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"globalroute__timing__hold__ws": {
@@ -64,7 +64,7 @@
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"compare": ">="
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},
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"detailedroute__route__wirelength": {
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"value": 52923,
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"value": 50927,
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"compare": "<="
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},
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"detailedroute__route__drc_errors": {
@@ -80,11 +80,11 @@
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"compare": "<="
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},
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"finish__timing__setup__ws": {
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"value": -116.0,
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"value": -98.4,
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"compare": ">="
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},
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"finish__timing__setup__tns": {
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"value": -3780.0,
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"value": -5410.0,
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"compare": ">="
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},
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"finish__timing__hold__ws": {

flow/designs/nangate45/swerv/config.mk

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@ export PLATFORM = nangate45
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export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/swerv_wrapper.sv2v.v
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export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
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7-
export CORE_UTILIZATION = 40
7+
export CORE_UTILIZATION = 65
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export CORE_ASPECT_RATIO = 1
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export CORE_MARGIN = 5
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flow/designs/nangate45/swerv/constraint.sdc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@ current_design swerv
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33
set clk_name core_clock
44
set clk_port_name clk
5-
set clk_period 2.0
5+
set clk_period 1.75
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set clk_io_pct 0.2
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set clk_port [get_ports $clk_port_name]

flow/designs/nangate45/swerv/rules-base.json

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -28,43 +28,43 @@
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"compare": "<="
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},
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"cts__timing__setup__ws": {
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"value": -0.207,
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"value": -0.387,
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"compare": ">="
3333
},
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"cts__timing__setup__tns": {
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"value": -9.64,
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"value": -233.0,
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"compare": ">="
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},
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"cts__timing__hold__ws": {
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"value": -0.1,
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"value": -0.0875,
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"compare": ">="
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},
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"cts__timing__hold__tns": {
43-
"value": -0.4,
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"value": -0.35,
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"compare": ">="
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},
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"globalroute__antenna_diodes_count": {
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"value": 102,
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"compare": "<="
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},
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"globalroute__timing__setup__ws": {
51-
"value": -0.224,
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"value": -0.416,
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"compare": ">="
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},
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"globalroute__timing__setup__tns": {
55-
"value": -37.0,
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"value": -305.0,
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"compare": ">="
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},
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"globalroute__timing__hold__ws": {
59-
"value": -0.1,
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"value": -0.0875,
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"compare": ">="
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},
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"globalroute__timing__hold__tns": {
63-
"value": -0.4,
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"value": -0.35,
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"compare": ">="
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},
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"detailedroute__route__wirelength": {
67-
"value": 2799467,
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"value": 2659376,
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"compare": "<="
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},
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"detailedroute__route__drc_errors": {
@@ -80,19 +80,19 @@
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"compare": "<="
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},
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"finish__timing__setup__ws": {
83-
"value": -0.235,
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"value": -0.398,
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"compare": ">="
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},
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"finish__timing__setup__tns": {
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"value": -23.9,
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"value": -234.0,
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"compare": ">="
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},
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"finish__timing__hold__ws": {
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"value": -0.1,
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"value": -0.0875,
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"compare": ">="
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},
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"finish__timing__hold__tns": {
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"value": -0.4,
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"value": -0.35,
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"compare": ">="
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},
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"finish__design__instance__area": {

flow/designs/sky130hd/chameleon/config.mk

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -29,8 +29,9 @@ export ABC_AREA = 1
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export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
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32-
export DIE_AREA = 0 0 2920 3520
33-
export CORE_AREA = 20 20 2900 3500
32+
export CORE_UTILIZATION = 70
33+
export CORE_ASPECT_RATIO = 1.3
34+
export CORE_MARGIN = 2
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3536
export chameleon_DIR = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)
3637

@@ -44,7 +45,7 @@ export ADDITIONAL_LEFS = $(chameleon_DIR)/lef/apb_sys_0.lef \
4445
$(chameleon_DIR)/lef/DMC_32x16HC.lef \
4546
$(chameleon_DIR)/lef/ibex_wrapper.lef
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47-
export MACRO_PLACEMENT_TCL = $(chameleon_DIR)/macro_placement.tcl
48+
#export MACRO_PLACEMENT_TCL = $(chameleon_DIR)/macro_placement.tcl
4849

4950
export FP_PDN_RAIL_WIDTH = 0.48
5051
export FP_PDN_RAIL_OFFSET = 0

flow/designs/sky130hd/chameleon/constraint.sdc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
set clk_name core_clock
22
set clk_port_name HCLK
3-
set clk_period 7.0
3+
set clk_period 3
44
set clk_io_pct 0.1
55

66
set clk_port [get_ports $clk_port_name]

flow/designs/sky130hd/chameleon/macro_placement.tcl

Lines changed: 0 additions & 6 deletions
This file was deleted.

flow/designs/sky130hd/chameleon/rules-base.json

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -8,63 +8,63 @@
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"compare": "=="
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},
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"placeopt__design__instance__area": {
11-
"value": 6528032,
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"value": 6489461,
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"compare": "<="
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},
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"placeopt__design__instance__count__stdcell": {
15-
"value": 69712,
15+
"value": 38946,
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"compare": "<="
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},
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"detailedplace__design__violations": {
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"value": 0,
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"compare": "=="
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},
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"cts__design__instance__count__setup_buffer": {
23-
"value": 6062,
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"value": 3387,
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"compare": "<="
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},
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"cts__design__instance__count__hold_buffer": {
27-
"value": 6062,
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"value": 3387,
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"compare": "<="
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},
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"cts__timing__setup__ws": {
31-
"value": -0.35,
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"value": -3.62,
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"compare": ">="
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},
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"cts__timing__setup__tns": {
35-
"value": -1.4,
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"value": -154.0,
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"compare": ">="
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},
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"cts__timing__hold__ws": {
39-
"value": -0.35,
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"value": -0.15,
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"compare": ">="
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},
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"cts__timing__hold__tns": {
43-
"value": -1.4,
43+
"value": -0.6,
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"compare": ">="
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},
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"globalroute__antenna_diodes_count": {
47-
"value": 154,
47+
"value": 100,
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"compare": "<="
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},
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"globalroute__timing__setup__ws": {
51-
"value": -0.35,
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"value": -3.22,
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"compare": ">="
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},
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"globalroute__timing__setup__tns": {
55-
"value": -1.4,
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"value": -138.0,
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"compare": ">="
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},
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"globalroute__timing__hold__ws": {
59-
"value": -0.35,
59+
"value": -0.15,
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"compare": ">="
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},
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"globalroute__timing__hold__tns": {
63-
"value": -1.4,
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"value": -0.6,
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"compare": ">="
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},
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"detailedroute__route__wirelength": {
67-
"value": 771372,
67+
"value": 680445,
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"compare": "<="
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},
7070
"detailedroute__route__drc_errors": {
@@ -76,27 +76,27 @@
7676
"compare": "<="
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},
7878
"detailedroute__antenna_diodes_count": {
79-
"value": 100,
79+
"value": 130,
8080
"compare": "<="
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},
8282
"finish__timing__setup__ws": {
83-
"value": -0.35,
83+
"value": -2.98,
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"compare": ">="
8585
},
8686
"finish__timing__setup__tns": {
87-
"value": -1.4,
87+
"value": -114.0,
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"compare": ">="
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},
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"finish__timing__hold__ws": {
91-
"value": -0.35,
91+
"value": -0.15,
9292
"compare": ">="
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},
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"finish__timing__hold__tns": {
95-
"value": -1.4,
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"value": -0.6,
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"compare": ">="
9797
},
9898
"finish__design__instance__area": {
99-
"value": 6531862,
99+
"value": 6493440,
100100
"compare": "<="
101101
}
102102
}

flow/designs/sky130hd/jpeg/config.mk

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@ export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*
66
export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include
77
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
88

9-
export CORE_UTILIZATION = 50
9+
export CORE_UTILIZATION = 55
1010
export PLACE_DENSITY_LB_ADDON = 0.15
1111
export TNS_END_PERCENT = 100
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