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Expand file tree Collapse file tree Original file line number Diff line number Diff line change @@ -8,10 +8,9 @@ export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.
88
99export ABC_AREA = 1
1010
11- export CORE_UTILIZATION = 40
11+ export CORE_UTILIZATION = 47
1212export CORE_ASPECT_RATIO = 1
1313export CORE_MARGIN = 2
14- export PLACE_DENSITY = 0.53
1514
1615export BLOCKS ?= aes_rcon aes_sbox
1716export SYNTH_HIERARCHICAL = 1
Original file line number Diff line number Diff line change 1212 "compare" : " <="
1313 },
1414 "placeopt__design__instance__count__stdcell" : {
15- "value" : 10573 ,
15+ "value" : 10501 ,
1616 "compare" : " <="
1717 },
1818 "detailedplace__design__violations" : {
1919 "value" : 0 ,
2020 "compare" : " =="
2121 },
2222 "cts__design__instance__count__setup_buffer" : {
23- "value" : 919 ,
23+ "value" : 913 ,
2424 "compare" : " <="
2525 },
2626 "cts__design__instance__count__hold_buffer" : {
27- "value" : 1286 ,
27+ "value" : 1691 ,
2828 "compare" : " <="
2929 },
3030 "cts__timing__setup__ws" : {
3131 "value" : -148.0 ,
3232 "compare" : " >="
3333 },
3434 "cts__timing__setup__tns" : {
35- "value" : -7820 .0 ,
35+ "value" : -12100 .0 ,
3636 "compare" : " >="
3737 },
3838 "cts__timing__hold__ws" : {
4848 "compare" : " <="
4949 },
5050 "globalroute__timing__setup__ws" : {
51- "value" : -150 .0 ,
51+ "value" : -133 .0 ,
5252 "compare" : " >="
5353 },
5454 "globalroute__timing__setup__tns" : {
55- "value" : -6750 .0 ,
55+ "value" : -9610 .0 ,
5656 "compare" : " >="
5757 },
5858 "globalroute__timing__hold__ws" : {
6464 "compare" : " >="
6565 },
6666 "detailedroute__route__wirelength" : {
67- "value" : 52923 ,
67+ "value" : 50927 ,
6868 "compare" : " <="
6969 },
7070 "detailedroute__route__drc_errors" : {
8080 "compare" : " <="
8181 },
8282 "finish__timing__setup__ws" : {
83- "value" : -116.0 ,
83+ "value" : -98.4 ,
8484 "compare" : " >="
8585 },
8686 "finish__timing__setup__tns" : {
87- "value" : -3780 .0 ,
87+ "value" : -5410 .0 ,
8888 "compare" : " >="
8989 },
9090 "finish__timing__hold__ws" : {
Original file line number Diff line number Diff line change @@ -4,7 +4,7 @@ export PLATFORM = nangate45
44export VERILOG_FILES = $(DESIGN_HOME ) /src/$(DESIGN_NAME ) /swerv_wrapper.sv2v.v
55export SDC_FILE = $(DESIGN_HOME ) /$(PLATFORM ) /$(DESIGN_NAME ) /constraint.sdc
66
7- export CORE_UTILIZATION = 40
7+ export CORE_UTILIZATION = 65
88export CORE_ASPECT_RATIO = 1
99export CORE_MARGIN = 5
1010
Original file line number Diff line number Diff line change @@ -2,7 +2,7 @@ current_design swerv
22
33set clk_name core_clock
44set clk_port_name clk
5- set clk_period 2.0
5+ set clk_period 1.75
66set clk_io_pct 0.2
77
88set clk_port [get_ports $clk_port_name ]
Original file line number Diff line number Diff line change 2828 "compare" : " <="
2929 },
3030 "cts__timing__setup__ws" : {
31- "value" : -0.207 ,
31+ "value" : -0.387 ,
3232 "compare" : " >="
3333 },
3434 "cts__timing__setup__tns" : {
35- "value" : -9.64 ,
35+ "value" : -233.0 ,
3636 "compare" : " >="
3737 },
3838 "cts__timing__hold__ws" : {
39- "value" : -0.1 ,
39+ "value" : -0.0875 ,
4040 "compare" : " >="
4141 },
4242 "cts__timing__hold__tns" : {
43- "value" : -0.4 ,
43+ "value" : -0.35 ,
4444 "compare" : " >="
4545 },
4646 "globalroute__antenna_diodes_count" : {
4747 "value" : 102 ,
4848 "compare" : " <="
4949 },
5050 "globalroute__timing__setup__ws" : {
51- "value" : -0.224 ,
51+ "value" : -0.416 ,
5252 "compare" : " >="
5353 },
5454 "globalroute__timing__setup__tns" : {
55- "value" : -37 .0 ,
55+ "value" : -305 .0 ,
5656 "compare" : " >="
5757 },
5858 "globalroute__timing__hold__ws" : {
59- "value" : -0.1 ,
59+ "value" : -0.0875 ,
6060 "compare" : " >="
6161 },
6262 "globalroute__timing__hold__tns" : {
63- "value" : -0.4 ,
63+ "value" : -0.35 ,
6464 "compare" : " >="
6565 },
6666 "detailedroute__route__wirelength" : {
67- "value" : 2799467 ,
67+ "value" : 2659376 ,
6868 "compare" : " <="
6969 },
7070 "detailedroute__route__drc_errors" : {
8080 "compare" : " <="
8181 },
8282 "finish__timing__setup__ws" : {
83- "value" : -0.235 ,
83+ "value" : -0.398 ,
8484 "compare" : " >="
8585 },
8686 "finish__timing__setup__tns" : {
87- "value" : -23.9 ,
87+ "value" : -234.0 ,
8888 "compare" : " >="
8989 },
9090 "finish__timing__hold__ws" : {
91- "value" : -0.1 ,
91+ "value" : -0.0875 ,
9292 "compare" : " >="
9393 },
9494 "finish__timing__hold__tns" : {
95- "value" : -0.4 ,
95+ "value" : -0.35 ,
9696 "compare" : " >="
9797 },
9898 "finish__design__instance__area" : {
Original file line number Diff line number Diff line change @@ -29,8 +29,9 @@ export ABC_AREA = 1
2929
3030export SDC_FILE = $(DESIGN_HOME ) /$(PLATFORM ) /$(DESIGN_NICKNAME ) /constraint.sdc
3131
32- export DIE_AREA = 0 0 2920 3520
33- export CORE_AREA = 20 20 2900 3500
32+ export CORE_UTILIZATION = 70
33+ export CORE_ASPECT_RATIO = 1.3
34+ export CORE_MARGIN = 2
3435
3536export chameleon_DIR = $(DESIGN_HOME ) /$(PLATFORM ) /$(DESIGN_NICKNAME )
3637
@@ -44,7 +45,7 @@ export ADDITIONAL_LEFS = $(chameleon_DIR)/lef/apb_sys_0.lef \
4445 $(chameleon_DIR ) /lef/DMC_32x16HC.lef \
4546 $(chameleon_DIR ) /lef/ibex_wrapper.lef
4647
47- export MACRO_PLACEMENT_TCL = $(chameleon_DIR ) /macro_placement.tcl
48+ # export MACRO_PLACEMENT_TCL = $(chameleon_DIR)/macro_placement.tcl
4849
4950export FP_PDN_RAIL_WIDTH = 0.48
5051export FP_PDN_RAIL_OFFSET = 0
Original file line number Diff line number Diff line change 11set clk_name core_clock
22set clk_port_name HCLK
3- set clk_period 7.0
3+ set clk_period 3
44set clk_io_pct 0.1
55
66set clk_port [get_ports $clk_port_name ]
Load Diff This file was deleted.
Original file line number Diff line number Diff line change 88 "compare" : " =="
99 },
1010 "placeopt__design__instance__area" : {
11- "value" : 6528032 ,
11+ "value" : 6489461 ,
1212 "compare" : " <="
1313 },
1414 "placeopt__design__instance__count__stdcell" : {
15- "value" : 69712 ,
15+ "value" : 38946 ,
1616 "compare" : " <="
1717 },
1818 "detailedplace__design__violations" : {
1919 "value" : 0 ,
2020 "compare" : " =="
2121 },
2222 "cts__design__instance__count__setup_buffer" : {
23- "value" : 6062 ,
23+ "value" : 3387 ,
2424 "compare" : " <="
2525 },
2626 "cts__design__instance__count__hold_buffer" : {
27- "value" : 6062 ,
27+ "value" : 3387 ,
2828 "compare" : " <="
2929 },
3030 "cts__timing__setup__ws" : {
31- "value" : -0.35 ,
31+ "value" : -3.62 ,
3232 "compare" : " >="
3333 },
3434 "cts__timing__setup__tns" : {
35- "value" : -1.4 ,
35+ "value" : -154.0 ,
3636 "compare" : " >="
3737 },
3838 "cts__timing__hold__ws" : {
39- "value" : -0.35 ,
39+ "value" : -0.15 ,
4040 "compare" : " >="
4141 },
4242 "cts__timing__hold__tns" : {
43- "value" : -1.4 ,
43+ "value" : -0.6 ,
4444 "compare" : " >="
4545 },
4646 "globalroute__antenna_diodes_count" : {
47- "value" : 154 ,
47+ "value" : 100 ,
4848 "compare" : " <="
4949 },
5050 "globalroute__timing__setup__ws" : {
51- "value" : -0.35 ,
51+ "value" : -3.22 ,
5252 "compare" : " >="
5353 },
5454 "globalroute__timing__setup__tns" : {
55- "value" : -1.4 ,
55+ "value" : -138.0 ,
5656 "compare" : " >="
5757 },
5858 "globalroute__timing__hold__ws" : {
59- "value" : -0.35 ,
59+ "value" : -0.15 ,
6060 "compare" : " >="
6161 },
6262 "globalroute__timing__hold__tns" : {
63- "value" : -1.4 ,
63+ "value" : -0.6 ,
6464 "compare" : " >="
6565 },
6666 "detailedroute__route__wirelength" : {
67- "value" : 771372 ,
67+ "value" : 680445 ,
6868 "compare" : " <="
6969 },
7070 "detailedroute__route__drc_errors" : {
7676 "compare" : " <="
7777 },
7878 "detailedroute__antenna_diodes_count" : {
79- "value" : 100 ,
79+ "value" : 130 ,
8080 "compare" : " <="
8181 },
8282 "finish__timing__setup__ws" : {
83- "value" : -0.35 ,
83+ "value" : -2.98 ,
8484 "compare" : " >="
8585 },
8686 "finish__timing__setup__tns" : {
87- "value" : -1.4 ,
87+ "value" : -114.0 ,
8888 "compare" : " >="
8989 },
9090 "finish__timing__hold__ws" : {
91- "value" : -0.35 ,
91+ "value" : -0.15 ,
9292 "compare" : " >="
9393 },
9494 "finish__timing__hold__tns" : {
95- "value" : -1.4 ,
95+ "value" : -0.6 ,
9696 "compare" : " >="
9797 },
9898 "finish__design__instance__area" : {
99- "value" : 6531862 ,
99+ "value" : 6493440 ,
100100 "compare" : " <="
101101 }
102102}
Original file line number Diff line number Diff line change @@ -6,7 +6,7 @@ export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*
66export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME ) /src/$(DESIGN_NICKNAME ) /include
77export SDC_FILE = $(DESIGN_HOME ) /$(PLATFORM ) /$(DESIGN_NICKNAME ) /constraint.sdc
88
9- export CORE_UTILIZATION = 50
9+ export CORE_UTILIZATION = 55
1010export PLACE_DENSITY_LB_ADDON = 0.15
1111export TNS_END_PERCENT = 100
1212
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