[Roadmap]: MORI 2026 H2 Roadmap

[TianDi101]

MORI Roadmap & Milestones – 2026 H2

Modeled on the AITER, ATOM, and vLLM AMD roadmaps. Last updated 2026-06-01.

Contributions and feedback are welcome.

Legend: ✓ done · ▶ in progress · ○ planned. Each item links a tracked PR/issue where available.

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Focus

• Distributed KV cache: HBM+DRAM tiered KV cache and NVMe-backed storage (GDS, SPDK) for large-context serving.
• SHMEM v2: Next-generation SHMEM implementation.
• Expert parallelism v2: Next-generation EP kernels (FLYDSL / C++) with elastic EP and fault tolerance.
• Rack-level enablement: Helios integration, cluster fault tolerance, and multi-tenant support across all three subsystems.

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H2 2026 (June → December)

MORI-UMBP

• Goal: Tiered KV storage (HBM → DRAM → NVMe) with scheduler-aware management and full rack-level reliability.
• Owners: @TianDi101 @maning00 @isytwu @zhangfei829 @inkcherry

KV Cache Management

• ○ KVCache management policy tuning
• ○ KVCache multi-pool support
• ○ SSD + SPDK/GDS enablement
• ○ Cluster fault tolerance
• ○ Multi-tenant support

System Integration

• ○ SGLang / vLLM integration & upstream
• ○ Scheduler – UMBP co-design
• ○ Helios enablement & tuning

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MORI-EP / SHMEM V2

• Goal: Next-generation EP and SHMEM kernels with elastic scaling and fault tolerance under production MoE workloads.
• Owners: @jhchouuu @zhangfei829 @wuyl1 @kawhil-amd @QizhouZhang97

Kernel Development

• ○ EP v2 kernel development (FLYDSL / C++)
• ○ SHMEM v2 (COO) development
• ○ Mega kernel codesign with FlyDSL
• ○ Engram support

Reliability & Scalability

• ○ Elastic EP / fault tolerance
• ○ EPLB enhancement

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MORI-Core (HW-SW Co-design)

• Goal: HW-SW co-design primitives enabling CPU- and GPU-initiated DMA / storage paths.

• Owners: @zhangfei829 @wuyl1

• ○ (TBD) CPU-initiated SDMA

• ○ (TBD) GPU-initiated NVMe

[functionstackx]

hi @TianDi101 can u add this to the roadmap? #367

[functionstackx]

hi @TianDi101 can u add this to the roadmap too? pytorch/pytorch#184147