From 6c382993579ef08367bf0e83d9f0fbd90e1be34e Mon Sep 17 00:00:00 2001 From: Kumonda221 Date: Fri, 3 Apr 2026 10:09:09 +0800 Subject: [PATCH 1/6] feat(TestTop): support for L2 Power Down --- src/test/scala/TestTop.scala | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/src/test/scala/TestTop.scala b/src/test/scala/TestTop.scala index 31812cf..803dfe1 100644 --- a/src/test/scala/TestTop.scala +++ b/src/test/scala/TestTop.scala @@ -199,6 +199,12 @@ class TestTopSoC(numCores: Int = 1, numULAgents: Int = 0, banks: Int = 1, issue: val l2Hint = Valid(new L2ToL1Hint) })) + val io_powerdown = IO(Vec(numCores, new Bundle { + val flushAll = Input(Bool()) + val flushAllDone = Output(Bool()) + val cpuHalt = Input(Bool()) + })) + val cycle = RegInit(0.U(64.W)) cycle := cycle + 1.U @@ -272,6 +278,10 @@ class TestTopSoC(numCores: Int = 1, numULAgents: Int = 0, banks: Int = 1, issue: dontTouch(l2.module.io) l2.module.io.l2_hint <> io_l1(i).l2Hint + + l2.module.io.l2Flush.foreach(_ := io_powerdown(i).flushAll) + io_powerdown(i).flushAllDone := l2.module.io.l2FlushDone.getOrElse(false.B) + l2.module.io_cpu_halt.foreach(_ := io_powerdown(i).cpuHalt) l2.module.io.hartId := i.U l2.module.io.pfCtrlFromCore := DontCare @@ -355,7 +365,10 @@ object TestTopSoCHelper { dataCheck = Some("oddparity"), // SAM for tester ICN: Home Node ID = 33 - sam = Seq(AddressSet.everything -> 33) + sam = Seq(AddressSet.everything -> 33), + + // L2 flush all + enableL2Flush = true ) case OpenLLCParamKey => OpenLLCParam( ways = 2, From 896511f1d2db4466e2569bf2e4dd8e42d1accefa Mon Sep 17 00:00:00 2001 From: Kumonda221 Date: Fri, 3 Apr 2026 10:38:33 +0800 Subject: [PATCH 2/6] submodule(CoupledL2): bump CoupledL2 --- coupledL2 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/coupledL2 b/coupledL2 index abf2f74..2bd7cbd 160000 --- a/coupledL2 +++ b/coupledL2 @@ -1 +1 @@ -Subproject commit abf2f7467f6b5666d2c3a6578ba8277cd7304696 +Subproject commit 2bd7cbd99e9da1ce9c1b96ba56b0a697aa5bf0b7 From 5c55d5a9cd7f24de627fb11dd2700ac27ff596cf Mon Sep 17 00:00:00 2001 From: Kumonda221 Date: Fri, 3 Apr 2026 17:58:38 +0800 Subject: [PATCH 3/6] feat(TestTop): add link down port --- src/test/scala/TestTop.scala | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/test/scala/TestTop.scala b/src/test/scala/TestTop.scala index 803dfe1..1766a8b 100644 --- a/src/test/scala/TestTop.scala +++ b/src/test/scala/TestTop.scala @@ -205,6 +205,8 @@ class TestTopSoC(numCores: Int = 1, numULAgents: Int = 0, banks: Int = 1, issue: val cpuHalt = Input(Bool()) })) + val io_linkdown = IO(Vec(numCores, Output(Bool()))) + val cycle = RegInit(0.U(64.W)) cycle := cycle + 1.U @@ -288,6 +290,10 @@ class TestTopSoC(numCores: Int = 1, numULAgents: Int = 0, banks: Int = 1, issue: l2.module.io_nodeID := i.U(NODEID_WIDTH.W) l2.module.io.debugTopDown := DontCare l2.module.io.l2_tlb_req <> DontCare + + io_linkdown(i) := !l2.module.io_chi.syscoreq && !l2.module.io_chi.syscoack && + !l2.module.io_chi.tx.linkactivereq && !l2.module.io_chi.tx.linkactiveack && + !l2.module.io_chi.rx.linkactivereq && !l2.module.io_chi.rx.linkactiveack } if (!l3Params.FPGAPlatform && l3Params.enableCHILog) { From 8f21a3af9f6cfeff53ed4d54b57a88dff9068116 Mon Sep 17 00:00:00 2001 From: Kumonda221 Date: Tue, 7 Apr 2026 16:33:28 +0800 Subject: [PATCH 4/6] feat(TestTop): support Seperate Reset --- src/test/scala/TestTop.scala | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/test/scala/TestTop.scala b/src/test/scala/TestTop.scala index 1766a8b..562c6d6 100644 --- a/src/test/scala/TestTop.scala +++ b/src/test/scala/TestTop.scala @@ -207,6 +207,8 @@ class TestTopSoC(numCores: Int = 1, numULAgents: Int = 0, banks: Int = 1, issue: val io_linkdown = IO(Vec(numCores, Output(Bool()))) + val io_resetsep = IO(Vec(numCores, Input(Bool()))) + val cycle = RegInit(0.U(64.W)) cycle := cycle + 1.U @@ -291,6 +293,8 @@ class TestTopSoC(numCores: Int = 1, numULAgents: Int = 0, banks: Int = 1, issue: l2.module.io.debugTopDown := DontCare l2.module.io.l2_tlb_req <> DontCare + l2.module.reset := io_resetsep(i) || reset.asBool + io_linkdown(i) := !l2.module.io_chi.syscoreq && !l2.module.io_chi.syscoack && !l2.module.io_chi.tx.linkactivereq && !l2.module.io_chi.tx.linkactiveack && !l2.module.io_chi.rx.linkactivereq && !l2.module.io_chi.rx.linkactiveack From a1eef7b716ee3a74584ca1923c00e5aca362f6aa Mon Sep 17 00:00:00 2001 From: Kumonda221 Date: Thu, 23 Apr 2026 18:38:09 +0800 Subject: [PATCH 5/6] feat(TestTop): CHI channel probes --- src/test/scala/TestTop.scala | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/src/test/scala/TestTop.scala b/src/test/scala/TestTop.scala index 562c6d6..55dccf5 100644 --- a/src/test/scala/TestTop.scala +++ b/src/test/scala/TestTop.scala @@ -205,6 +205,21 @@ class TestTopSoC(numCores: Int = 1, numULAgents: Int = 0, banks: Int = 1, issue: val cpuHalt = Input(Bool()) })) + val io_probe_chi = IO(Vec(numCores, new Bundle { + val txreq_flit = Output(UInt((new CHIREQ).getWidth.W)) + val txrsp_flit = Output(UInt((new CHIRSP).getWidth.W)) + val txdat_flit = Output(UInt((new CHIDAT).getWidth.W)) + val rxsnp_flit = Output(UInt((new CHISNP).getWidth.W)) + val rxrsp_flit = Output(UInt((new CHIRSP).getWidth.W)) + val rxdat_flit = Output(UInt((new CHIDAT).getWidth.W)) + val txreq_flitv = Output(Bool()) + val txrsp_flitv = Output(Bool()) + val txdat_flitv = Output(Bool()) + val rxsnp_flitv = Output(Bool()) + val rxrsp_flitv = Output(Bool()) + val rxdat_flitv = Output(Bool()) + })) + val io_linkdown = IO(Vec(numCores, Output(Bool()))) val io_resetsep = IO(Vec(numCores, Input(Bool()))) @@ -261,6 +276,20 @@ class TestTopSoC(numCores: Int = 1, numULAgents: Int = 0, banks: Int = 1, issue: l2_nodes.zipWithIndex.foreach { case (l2, i) => + io_probe_chi(i).txreq_flit := l2.module.io_chi.tx.req.flit + io_probe_chi(i).txrsp_flit := l2.module.io_chi.tx.rsp.flit + io_probe_chi(i).txdat_flit := l2.module.io_chi.tx.dat.flit + io_probe_chi(i).rxsnp_flit := l2.module.io_chi.rx.snp.flit + io_probe_chi(i).rxrsp_flit := l2.module.io_chi.rx.rsp.flit + io_probe_chi(i).rxdat_flit := l2.module.io_chi.rx.dat.flit + + io_probe_chi(i).txreq_flitv := l2.module.io_chi.tx.req.flitv + io_probe_chi(i).txrsp_flitv := l2.module.io_chi.tx.rsp.flitv + io_probe_chi(i).txdat_flitv := l2.module.io_chi.tx.dat.flitv + io_probe_chi(i).rxsnp_flitv := l2.module.io_chi.rx.snp.flitv + io_probe_chi(i).rxrsp_flitv := l2.module.io_chi.rx.rsp.flitv + io_probe_chi(i).rxdat_flitv := l2.module.io_chi.rx.dat.flitv + if (!l3Params.FPGAPlatform && l3Params.enableCHILog) { CLogB.logFlitsRNOfRNF( id = clogIdUpstream, From 949b45393924927d772d16c10e68b08a7d79fd8f Mon Sep 17 00:00:00 2001 From: Kumonda221 Date: Thu, 23 Apr 2026 18:40:01 +0800 Subject: [PATCH 6/6] chore(TestTop): tweaked sizes of CoupledL2 and OpenLLC --- src/test/scala/TestTop.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/test/scala/TestTop.scala b/src/test/scala/TestTop.scala index 55dccf5..f72c171 100644 --- a/src/test/scala/TestTop.scala +++ b/src/test/scala/TestTop.scala @@ -257,7 +257,7 @@ class TestTopSoC(numCores: Int = 1, numULAgents: Int = 0, banks: Int = 1, issue: val l3 = Module(new OpenLLC()(new Config((site, here, up) => { case CHIIssue => issue case OpenLLCParamKey => l3Params.copy( - clientCaches = Seq.fill(numCores)(l2Params.copy(ways = 2, sets = 2)), + clientCaches = Seq.fill(numCores)(l2Params.copy(ways = 4, sets = 16)), fullAddressBits = ADDR_WIDTH, hartIds = 0 until numCores ) @@ -389,7 +389,7 @@ object TestTopSoCHelper { val config = new Config((_, _, _) => { case L2ParamKey => L2Param( ways = 4, - sets = 128, + sets = 16, clientCaches = Seq(L1Param(aliasBitsOpt = Some(2))), // echoField = Seq(DirtyField), enablePerf = enablePerf, @@ -410,8 +410,8 @@ object TestTopSoCHelper { enableL2Flush = true ) case OpenLLCParamKey => OpenLLCParam( - ways = 2, - sets = 2, + ways = 4, + sets = 32, banks = 1, clientCaches = Seq(L2Param()), enablePerf = enablePerf,