diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h
index 9586027..a6a5bbc 100644
--- a/src/iss/arch/riscv_hart_m_p.h
+++ b/src/iss/arch/riscv_hart_m_p.h
@@ -338,8 +338,8 @@ template <typename BASE, features_e FEAT> void riscv_hart_m_p<BASE, FEAT>::check
     bool mstatus_mie = this->state.mstatus.MIE;
     auto m_enabled = this->reg.PRIV < PRIV_M || mstatus_mie;
     auto enabled_interrupts = m_enabled ? ena_irq : 0;
-
-    if(enabled_interrupts != 0) {
+    this->reg.pending_trap = 0;
+    if(enabled_interrupts) {
         int res = 0;
         while((enabled_interrupts & 1) == 0) {
             enabled_interrupts >>= 1;
diff --git a/src/sysc/core2sc_adapter.h b/src/sysc/core2sc_adapter.h
index 7c0c2ef..bf2851c 100644
--- a/src/sysc/core2sc_adapter.h
+++ b/src/sysc/core2sc_adapter.h
@@ -321,7 +321,13 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
             this->csr[iss::arch::mip] &= ~mask;
         this->check_interrupt();
         if(value)
-            SCCTRACE(owner->hier_name()) << "Triggering interrupt " << id << " Pending trap: " << this->reg.pending_trap;
+            SCCTRACE(owner->hier_name()) << "Triggering interrupt " << id
+#ifndef NDEBUG
+                                         << " (Pending trap: " << std::hex << "0x"
+                                         << ((this->reg.pending_trap >> 16) & 0xff) // 0x80 << 24 | (cause << 16) | trap_id
+                                         << ")"
+#endif
+                ;
     }
 
     void _local_irq_mt(short id, bool value) {