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Update Memory.scala
1 parent d187a1f commit 3a1bdc9

1 file changed

Lines changed: 24 additions & 18 deletions

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src/main/scala/RISCV/Memory.scala

Lines changed: 24 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -24,39 +24,45 @@ class Memory() extends Module {
2424
})
2525

2626
val memory = SyncReadMem(1024, UInt(32.W))
27-
loadMemoryFromFileInline(memory, "program.hex")
27+
loadMemoryFromFileInline(memory, "program.hex")
2828

2929
io.address_vga := 0.U
3030
io.write_vga := true.B
3131
io.write_value_vga := 0.U
32-
io.read_value_1 := 0.U
33-
io.read_value_2 := 0.U
32+
io.read_value_1 := 0.U
33+
io.read_value_2 := 0.U
3434

35-
val isVGA = io.address_1 >= 0b1000000000000.U;
36-
io.address_vga := Mux(isVGA, io.address_1 - 0b1000000000000.U,0.U);
37-
io.write_vga := isVGA && io.write_1
35+
val isVGA = io.address_1 >= 0b1000000000000.U;
36+
io.address_vga := Mux(isVGA, io.address_1 - 0b1000000000000.U, 0.U);
37+
io.write_vga := isVGA && io.write_1
3838
io.write_value_vga := io.write_value_1
3939

4040
when(isVGA) {
4141
printf(
42-
"Writing to VGA! Address: %b Data: %b\n",
43-
io.address_1 - 0b1000000000000.U,
44-
io.write_value_1
42+
"Writing to VGA! Address: %b Data: %b\n",
43+
io.address_1 - 0b1000000000000.U,
44+
io.write_value_1
45+
);
46+
}.otherwise {
47+
printf(
48+
"Writing to VGA! Memory: %b Data: %b\n",
49+
io.address_1 - 0b1000000000000.U,
50+
io.write_value_1
4551
);
4652
}
4753

4854
io.read_value_1 := memory.readWrite(
49-
io.address_1,
50-
io.write_value_1,
51-
(io.read_1 || io.write_1) && !isVGA,
52-
io.write_1
55+
io.address_1,
56+
io.write_value_1,
57+
(io.read_1 || io.write_1) && !isVGA,
58+
io.write_1
5359
)
5460

5561
io.read_value_2 := memory.readWrite(
56-
io.address_2,
57-
io.write_value_2,
58-
(io.read_2 || io.write_2) && !isVGA,
59-
io.write_2
62+
io.address_2,
63+
io.write_value_2,
64+
(io.read_2 || io.write_2) && !isVGA,
65+
io.write_2
6066
)
61-
67+
6268
}

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