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tu: Disable LRZ properly on A7XX
LRZ wasn't entirely disabled due to the register `A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO` not being set to `0` in all circumstances, this register affects rendering even when LRZ is disabled so needs to be set to `0` until LRZ is properly implemented. Signed-off-by: Mark Collins <mark@igalia.com>
1 parent 8071ef6 commit 650d7fd

5 files changed

Lines changed: 51 additions & 24 deletions

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‎src/freedreno/registers/adreno/a6xx.xml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2104,7 +2104,7 @@ to upconvert to 32b float internally?
21042104
<!-- A bit tentative but it's a color and it is followed by LRZ_CLEAR -->
21052105
<reg32 offset="0x8111" name="GRAS_LRZ_CLEAR_DEPTH_F32" type="float" variants="A7XX-"/>
21062106

2107-
<reg32 offset="0x8113" name="GRAS_UNKNOWN_8113" variants="A7XX-" usage="rp_blit"/>
2107+
<reg32 offset="0x8113" name="GRAS_LRZ_DEPTH_BUFFER_INFO" variants="A7XX-" usage="rp_blit"/>
21082108

21092109
<!-- Always written together and always equal 09510840 00000a62 -->
21102110
<reg32 offset="0x8120" name="GRAS_UNKNOWN_8120" variants="A7XX-" usage="cmd"/>

‎src/freedreno/vulkan/tu_clear_blit.cc‎

Lines changed: 10 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1298,6 +1298,7 @@ r3d_src_gmem(struct tu_cmd_buffer *cmd,
12981298
r3d_src_common(cmd, cs, desc, 0, 0, VK_FILTER_NEAREST);
12991299
}
13001300

1301+
template <chip CHIP>
13011302
static void
13021303
r3d_dst(struct tu_cs *cs, const struct fdl6_view *iview, uint32_t layer,
13031304
enum pipe_format src_format)
@@ -1319,6 +1320,9 @@ r3d_dst(struct tu_cs *cs, const struct fdl6_view *iview, uint32_t layer,
13191320
tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_FLAG_BUFFER(0), 3);
13201321
tu_cs_image_flag_ref(cs, iview, layer);
13211322

1323+
if (CHIP >= A7XX)
1324+
tu_cs_emit_regs(cs, A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO(0));
1325+
13221326
/* Use color format from RB_MRT_BUF_INFO. This register is relevant for
13231327
* FMT6_NV12_Y.
13241328
*/
@@ -1626,7 +1630,7 @@ static const struct blit_ops r3d_ops = {
16261630
.clear_value = r3d_clear_value,
16271631
.src = r3d_src,
16281632
.src_buffer = r3d_src_buffer<CHIP>,
1629-
.dst = r3d_dst,
1633+
.dst = r3d_dst<CHIP>,
16301634
.dst_depth = r3d_dst_depth,
16311635
.dst_stencil = r3d_dst_stencil,
16321636
.dst_buffer = r3d_dst_buffer,
@@ -1983,7 +1987,7 @@ tu_CmdBlitImage2(VkCommandBuffer commandBuffer,
19831987
}
19841988

19851989
if (dst_image->lrz_height) {
1986-
tu_disable_lrz(cmd, &cmd->cs, dst_image);
1990+
tu_disable_lrz<CHIP>(cmd, &cmd->cs, dst_image);
19871991
}
19881992
}
19891993
TU_GENX(tu_CmdBlitImage2);
@@ -2101,7 +2105,7 @@ tu_CmdCopyBufferToImage2(VkCommandBuffer commandBuffer,
21012105
pCopyBufferToImageInfo->pRegions + i);
21022106

21032107
if (dst_image->lrz_height) {
2104-
tu_disable_lrz(cmd, &cmd->cs, dst_image);
2108+
tu_disable_lrz<CHIP>(cmd, &cmd->cs, dst_image);
21052109
}
21062110
}
21072111
TU_GENX(tu_CmdCopyBufferToImage2);
@@ -2445,7 +2449,7 @@ tu_CmdCopyImage2(VkCommandBuffer commandBuffer,
24452449
}
24462450

24472451
if (dst_image->lrz_height) {
2448-
tu_disable_lrz(cmd, &cmd->cs, dst_image);
2452+
tu_disable_lrz<CHIP>(cmd, &cmd->cs, dst_image);
24492453
}
24502454
}
24512455
TU_GENX(tu_CmdCopyImage2);
@@ -2808,7 +2812,7 @@ tu_CmdClearDepthStencilImage(VkCommandBuffer commandBuffer,
28082812
clear_image<CHIP>(cmd, image, (const VkClearValue*) pDepthStencil, range, range->aspectMask);
28092813
}
28102814

2811-
tu_lrz_clear_depth_image(cmd, image, pDepthStencil, rangeCount, pRanges);
2815+
tu_lrz_clear_depth_image<CHIP>(cmd, image, pDepthStencil, rangeCount, pRanges);
28122816
}
28132817
TU_GENX(tu_CmdClearDepthStencilImage);
28142818

@@ -3765,7 +3769,7 @@ store_3d_blit(struct tu_cmd_buffer *cmd,
37653769
r3d_dst_stencil(cs, iview, layer);
37663770
}
37673771
} else {
3768-
r3d_dst(cs, &iview->view, layer, src_format);
3772+
r3d_dst<CHIP>(cs, &iview->view, layer, src_format);
37693773
}
37703774

37713775
r3d_src_gmem<CHIP>(cmd, cs, iview, src_format, dst_format, gmem_offset, cpp);

‎src/freedreno/vulkan/tu_cmd_buffer.cc‎

Lines changed: 5 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1681,7 +1681,7 @@ tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
16811681
{
16821682
const struct tu_framebuffer *fb = cmd->state.framebuffer;
16831683

1684-
tu_lrz_sysmem_begin(cmd, cs);
1684+
tu_lrz_sysmem_begin<CHIP>(cmd, cs);
16851685

16861686
assert(fb->width > 0 && fb->height > 0);
16871687
tu6_emit_window_scissor(cs, 0, 0, fb->width - 1, fb->height - 1);
@@ -1700,10 +1700,8 @@ tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
17001700
tu_cs_emit_regs(cs,
17011701
A7XX_RB_UNKNOWN_8E06(0x2080000));
17021702

1703-
/* These three have something to do with lrz/depth */
17041703
tu_cs_emit_regs(cs, A7XX_GRAS_UNKNOWN_8007(0x0));
17051704
tu_cs_emit_regs(cs, A7XX_GRAS_UNKNOWN_810B(0x3));
1706-
tu_cs_emit_regs(cs, A7XX_GRAS_UNKNOWN_8113(0x4));
17071705

17081706
tu_cs_emit_regs(cs, A6XX_GRAS_UNKNOWN_8110(0x2));
17091707
tu_cs_emit_regs(cs, A7XX_RB_UNKNOWN_8E09(0x4));
@@ -1758,7 +1756,7 @@ tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
17581756
{
17591757
struct tu_physical_device *phys_dev = cmd->device->physical_device;
17601758
const struct tu_tiling_config *tiling = cmd->state.tiling;
1761-
tu_lrz_tiling_begin(cmd, cs);
1759+
tu_lrz_tiling_begin<CHIP>(cmd, cs);
17621760

17631761
if (CHIP >= A7XX) {
17641762
tu_cs_emit_pkt7(cs, CP_THREAD_CONTROL, 1);
@@ -1771,8 +1769,6 @@ tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
17711769
A7XX_RB_UNKNOWN_8E06(0x0));
17721770

17731771
tu_cs_emit_regs(cs, A7XX_GRAS_UNKNOWN_8007(0x0));
1774-
tu_cs_emit_regs(cs, A7XX_GRAS_UNKNOWN_810B(0x0));
1775-
tu_cs_emit_regs(cs, A7XX_GRAS_UNKNOWN_8113(0x0));
17761772

17771773
tu_cs_emit_regs(cs, A6XX_GRAS_UNKNOWN_8110(0x2));
17781774
tu_cs_emit_regs(cs, A7XX_RB_UNKNOWN_8E09(0x4));
@@ -1895,7 +1891,7 @@ tu6_tile_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
18951891

18961892
tu_cs_emit_call(cs, &cmd->draw_epilogue_cs);
18971893

1898-
tu_lrz_tiling_end(cmd, cs);
1894+
tu_lrz_tiling_end<CHIP>(cmd, cs);
18991895

19001896
tu_emit_event_write<CHIP>(cmd, cs, FD_CCU_FLUSH_BLIT_CACHE);
19011897

@@ -4090,7 +4086,7 @@ tu_CmdBeginRenderPass2(VkCommandBuffer commandBuffer,
40904086
if (pass->subpasses[0].feedback_invalidate)
40914087
cmd->state.renderpass_cache.flush_bits |= TU_CMD_FLAG_CACHE_INVALIDATE;
40924088

4093-
tu_lrz_begin_renderpass(cmd);
4089+
tu_lrz_begin_renderpass<CHIP>(cmd);
40944090

40954091
cmd->trace_renderpass_start = u_trace_end_iterator(&cmd->trace);
40964092

@@ -4207,7 +4203,7 @@ tu_CmdBeginRendering(VkCommandBuffer commandBuffer,
42074203
if (resuming)
42084204
tu_lrz_begin_resumed_renderpass(cmd);
42094205
else
4210-
tu_lrz_begin_renderpass(cmd);
4206+
tu_lrz_begin_renderpass<CHIP>(cmd);
42114207
}
42124208

42134209

‎src/freedreno/vulkan/tu_lrz.cc‎

Lines changed: 29 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,7 @@
5151
* before using LRZ.
5252
*/
5353

54+
template <chip CHIP>
5455
static void
5556
tu6_emit_lrz_buffer(struct tu_cs *cs, struct tu_image *depth_image)
5657
{
@@ -59,6 +60,10 @@ tu6_emit_lrz_buffer(struct tu_cs *cs, struct tu_image *depth_image)
5960
A6XX_GRAS_LRZ_BUFFER_BASE(0),
6061
A6XX_GRAS_LRZ_BUFFER_PITCH(0),
6162
A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
63+
64+
if (CHIP >= A7XX)
65+
tu_cs_emit_regs(cs, A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO(0));
66+
6267
return;
6368
}
6469

@@ -71,6 +76,10 @@ tu6_emit_lrz_buffer(struct tu_cs *cs, struct tu_image *depth_image)
7176
A6XX_GRAS_LRZ_BUFFER_BASE(.qword = lrz_iova),
7277
A6XX_GRAS_LRZ_BUFFER_PITCH(.pitch = depth_image->lrz_pitch),
7378
A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(.qword = lrz_fc_iova));
79+
80+
if (CHIP >= A7XX)
81+
// TODO: Figure out the correct value to set here.
82+
tu_cs_emit_regs(cs, A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO(0));
7483
}
7584

7685
static void
@@ -215,6 +224,7 @@ tu_lrz_begin_resumed_renderpass(struct tu_cmd_buffer *cmd)
215224
}
216225
}
217226

227+
template <chip CHIP>
218228
void
219229
tu_lrz_begin_renderpass(struct tu_cmd_buffer *cmd)
220230
{
@@ -238,7 +248,7 @@ tu_lrz_begin_renderpass(struct tu_cmd_buffer *cmd)
238248

239249
for (unsigned i = 0; i < pass->attachment_count; i++) {
240250
struct tu_image *image = cmd->state.attachments[i]->image;
241-
tu_disable_lrz(cmd, &cmd->cs, image);
251+
tu_disable_lrz<CHIP>(cmd, &cmd->cs, image);
242252
}
243253

244254
/* We need a valid LRZ fast-clear base, in case the render pass contents
@@ -254,9 +264,10 @@ tu_lrz_begin_renderpass(struct tu_cmd_buffer *cmd)
254264
tu_lrz_begin_resumed_renderpass(cmd);
255265

256266
if (!cmd->state.lrz.valid) {
257-
tu6_emit_lrz_buffer(&cmd->cs, NULL);
267+
tu6_emit_lrz_buffer<CHIP>(&cmd->cs, NULL);
258268
}
259269
}
270+
TU_GENX(tu_lrz_begin_renderpass);
260271

261272
void
262273
tu_lrz_begin_secondary_cmdbuf(struct tu_cmd_buffer *cmd)
@@ -269,6 +280,7 @@ tu_lrz_begin_secondary_cmdbuf(struct tu_cmd_buffer *cmd)
269280
}
270281
}
271282

283+
template <chip CHIP>
272284
void
273285
tu_lrz_tiling_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
274286
{
@@ -282,7 +294,7 @@ tu_lrz_tiling_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
282294

283295
struct tu_lrz_state *lrz = &cmd->state.lrz;
284296

285-
tu6_emit_lrz_buffer(cs, lrz->image_view->image);
297+
tu6_emit_lrz_buffer<CHIP>(cs, lrz->image_view->image);
286298

287299
if (lrz->reuse_previous_state) {
288300
/* Reuse previous LRZ state, LRZ cache is assumed to be
@@ -338,12 +350,14 @@ tu_lrz_tiling_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
338350
}
339351
}
340352
}
353+
TU_GENX(tu_lrz_tiling_begin);
341354

355+
template <chip CHIP>
342356
void
343357
tu_lrz_tiling_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
344358
{
345359
if (cmd->state.lrz.fast_clear || cmd->state.lrz.gpu_dir_tracking) {
346-
tu6_emit_lrz_buffer(cs, cmd->state.lrz.image_view->image);
360+
tu6_emit_lrz_buffer<CHIP>(cs, cmd->state.lrz.image_view->image);
347361

348362
if (cmd->state.lrz.gpu_dir_tracking) {
349363
tu6_write_lrz_reg(cmd, &cmd->cs,
@@ -373,7 +387,9 @@ tu_lrz_tiling_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
373387
* reason to do such clear.
374388
*/
375389
}
390+
TU_GENX(tu_lrz_tiling_end);
376391

392+
template <chip CHIP>
377393
void
378394
tu_lrz_sysmem_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
379395
{
@@ -387,12 +403,12 @@ tu_lrz_sysmem_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
387403
struct tu_lrz_state *lrz = &cmd->state.lrz;
388404

389405
if (cmd->device->physical_device->info->a6xx.has_lrz_dir_tracking) {
390-
tu_disable_lrz(cmd, cs, lrz->image_view->image);
406+
tu_disable_lrz<CHIP>(cmd, cs, lrz->image_view->image);
391407
/* Make sure depth view comparison will fail. */
392408
tu6_write_lrz_reg(cmd, cs,
393409
A6XX_GRAS_LRZ_DEPTH_VIEW(.dword = 0));
394410
} else {
395-
tu6_emit_lrz_buffer(cs, lrz->image_view->image);
411+
tu6_emit_lrz_buffer<CHIP>(cs, lrz->image_view->image);
396412
/* Even though we disable LRZ writes in sysmem mode - there is still
397413
* LRZ test, so LRZ should be cleared.
398414
*/
@@ -408,6 +424,7 @@ tu_lrz_sysmem_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
408424
}
409425
}
410426
}
427+
TU_GENX(tu_lrz_sysmem_begin);
411428

412429
void
413430
tu_lrz_sysmem_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
@@ -416,6 +433,7 @@ tu_lrz_sysmem_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
416433
}
417434

418435
/* Disable LRZ outside of renderpass. */
436+
template <chip CHIP>
419437
void
420438
tu_disable_lrz(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
421439
struct tu_image *image)
@@ -426,11 +444,13 @@ tu_disable_lrz(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
426444
if (!image->lrz_height)
427445
return;
428446

429-
tu6_emit_lrz_buffer(cs, image);
447+
tu6_emit_lrz_buffer<CHIP>(cs, image);
430448
tu6_disable_lrz_via_depth_view(cmd, cs);
431449
}
450+
TU_GENX(tu_disable_lrz);
432451

433452
/* Clear LRZ, used for out of renderpass depth clears. */
453+
template <chip CHIP>
434454
void
435455
tu_lrz_clear_depth_image(struct tu_cmd_buffer *cmd,
436456
struct tu_image *image,
@@ -460,7 +480,7 @@ tu_lrz_clear_depth_image(struct tu_cmd_buffer *cmd,
460480
bool fast_clear = image->lrz_fc_size && (pDepthStencil->depth == 0.f ||
461481
pDepthStencil->depth == 1.f);
462482

463-
tu6_emit_lrz_buffer(&cmd->cs, image);
483+
tu6_emit_lrz_buffer<CHIP>(&cmd->cs, image);
464484

465485
tu6_write_lrz_reg(cmd, &cmd->cs, A6XX_GRAS_LRZ_DEPTH_VIEW(
466486
.base_layer = range->baseArrayLayer,
@@ -481,6 +501,7 @@ tu_lrz_clear_depth_image(struct tu_cmd_buffer *cmd,
481501
tu6_clear_lrz<A6XX>(cmd, &cmd->cs, image, (const VkClearValue*) pDepthStencil);
482502
}
483503
}
504+
TU_GENX(tu_lrz_clear_depth_image);
484505

485506
void
486507
tu_lrz_disable_during_renderpass(struct tu_cmd_buffer *cmd)

‎src/freedreno/vulkan/tu_lrz.h‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -45,17 +45,20 @@ struct tu_lrz_state
4545
void
4646
tu6_emit_lrz(struct tu_cmd_buffer *cmd, struct tu_cs *cs);
4747

48+
template <chip CHIP>
4849
void
4950
tu_disable_lrz(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
5051
struct tu_image *image);
5152

53+
template <chip CHIP>
5254
void
5355
tu_lrz_clear_depth_image(struct tu_cmd_buffer *cmd,
5456
struct tu_image *image,
5557
const VkClearDepthStencilValue *pDepthStencil,
5658
uint32_t rangeCount,
5759
const VkImageSubresourceRange *pRanges);
5860

61+
template <chip CHIP>
5962
void
6063
tu_lrz_begin_renderpass(struct tu_cmd_buffer *cmd);
6164

@@ -65,12 +68,15 @@ tu_lrz_begin_resumed_renderpass(struct tu_cmd_buffer *cmd);
6568
void
6669
tu_lrz_begin_secondary_cmdbuf(struct tu_cmd_buffer *cmd);
6770

71+
template <chip CHIP>
6872
void
6973
tu_lrz_tiling_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs);
7074

75+
template <chip CHIP>
7176
void
7277
tu_lrz_tiling_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs);
7378

79+
template <chip CHIP>
7480
void
7581
tu_lrz_sysmem_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs);
7682

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